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authorFrancisco Jerez <[email protected]>2013-09-25 16:31:35 -0700
committerFrancisco Jerez <[email protected]>2013-11-04 12:12:38 -0800
commitba885c30c74f9efc94743d4582d30a0e70924b97 (patch)
treec1fbbdb4f55d1de6d5e24dc74232382f5b635aca /src/mesa/drivers/dri/i965/brw_vec4.h
parent764f40d92edfdfea4ea2b092fd1ba7888cc7ea7e (diff)
i965/gen7: Handle atomic instructions from the VEC4 back-end.
This can deal with all the 15 32-bit untyped atomic operations the hardware supports, but only INC and PREDEC are going to be exposed through the API for now. v2: Represent atomics as GLSL intrinsics. Add support for variably indexed atomic counter arrays. v3: Add comment on why we don't need to assign uniform storage for atomic counters. Reviewed-by: Paul Berry <[email protected]>
Diffstat (limited to 'src/mesa/drivers/dri/i965/brw_vec4.h')
-rw-r--r--src/mesa/drivers/dri/i965/brw_vec4.h9
1 files changed, 9 insertions, 0 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_vec4.h b/src/mesa/drivers/dri/i965/brw_vec4.h
index a479646c69b..1f29e576caf 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4.h
+++ b/src/mesa/drivers/dri/i965/brw_vec4.h
@@ -489,6 +489,13 @@ public:
void emit_shader_time_write(enum shader_time_shader_type type,
src_reg value);
+ void emit_untyped_atomic(unsigned atomic_op, unsigned surf_index,
+ dst_reg dst, src_reg offset, src_reg src0,
+ src_reg src1);
+
+ void emit_untyped_surface_read(unsigned surf_index, dst_reg dst,
+ src_reg offset);
+
src_reg get_scratch_offset(vec4_instruction *inst,
src_reg *reladdr, int reg_offset);
src_reg get_pull_constant_offset(vec4_instruction *inst,
@@ -514,6 +521,8 @@ public:
void dump_instruction(backend_instruction *inst);
+ void visit_atomic_counter_intrinsic(ir_call *ir);
+
protected:
void emit_vertex();
void lower_attributes_to_hw_regs(const int *attribute_map,