i965: Push miptree tiling request into flags

With the last few patches a way was provided to influence lower layer miptree
layout and allocation decisions via flags (replacing bools). For simplicity, I
chose not to touch the tiling requests because the change was slightly less
mechanical than replacing the bools.

The goal is to organize the code so we can continue to add new parameters and
tiling types while minimizing risk to the existing code, and not having to
constantly add new function parameters.

v2: Rebased on Anuj's recent Yf/Ys changes
Fix non-msrt MCS allocation (was only happening in gen8 case before)

v3: small fix in assertion requested by Chad

v4: Use parens to get the order right from v3.

Signed-off-by: Ben Widawsky <[email protected]>
Reviewed-by: Jordan Justen <[email protected]>

1 files changed, 11 insertions, 10 deletions

diff --git a/src/mesa/drivers/dri/i965/brw_tex_layout.c b/src/mesa/drivers/dri/i965/brw_tex_layout.c
index 389834f012a..a12b4af579e 100644
--- a/src/mesa/drivers/dri/i965/brw_tex_layout.c
+++ b/src/mesa/drivers/dri/i965/brw_tex_layout.c
@@ -614,8 +614,8 @@ brw_miptree_layout_texture_3d(struct brw_context *brw,
  */
 static uint32_t
 brw_miptree_choose_tiling(struct brw_context *brw,
-                          enum intel_miptree_tiling_mode requested,
-                          const struct intel_mipmap_tree *mt)
+                          const struct intel_mipmap_tree *mt,
+                          uint32_t layout_flags)
 {
    if (mt->format == MESA_FORMAT_S_UINT8) {
       /* The stencil buffer is W tiled. However, we request from the kernel a
@@ -624,15 +624,18 @@ brw_miptree_choose_tiling(struct brw_context *brw,
       return I915_TILING_NONE;
    }
 
+   /* Do not support changing the tiling for miptrees with pre-allocated BOs. */
+   assert((layout_flags & MIPTREE_LAYOUT_FOR_BO) == 0);
+
    /* Some usages may want only one type of tiling, like depth miptrees (Y
     * tiled), or temporary BOs for uploading data once (linear).
     */
-   switch (requested) {
-   case INTEL_MIPTREE_TILING_ANY:
+   switch (layout_flags & MIPTREE_LAYOUT_ALLOC_ANY_TILED) {
+   case MIPTREE_LAYOUT_ALLOC_ANY_TILED:
       break;
-   case INTEL_MIPTREE_TILING_Y:
+   case MIPTREE_LAYOUT_ALLOC_YTILED:
       return I915_TILING_Y;
-   case INTEL_MIPTREE_TILING_NONE:
+   case MIPTREE_LAYOUT_ALLOC_LINEAR:
       return I915_TILING_NONE;
    }
 
@@ -835,7 +838,6 @@ intel_miptree_can_use_tr_mode(const struct intel_mipmap_tree *mt)
 void
 brw_miptree_layout(struct brw_context *brw,
                    struct intel_mipmap_tree *mt,
-                   enum intel_miptree_tiling_mode requested,
                    uint32_t layout_flags)
 {
    const unsigned bpp = mt->cpp * 8;
@@ -852,8 +854,7 @@ brw_miptree_layout(struct brw_context *brw,
       !(layout_flags & MIPTREE_LAYOUT_FOR_BO) &&
       !mt->compressed &&
       _mesa_is_format_color_format(mt->format) &&
-      (requested == INTEL_MIPTREE_TILING_Y ||
-       requested == INTEL_MIPTREE_TILING_ANY) &&
+      (layout_flags & MIPTREE_LAYOUT_ALLOC_YTILED) &&
       (bpp && is_power_of_two(bpp)) &&
       /* FIXME: To avoid piglit regressions keep the Yf/Ys tiling
        * disabled at the moment.
@@ -897,7 +898,7 @@ brw_miptree_layout(struct brw_context *brw,
       if (layout_flags & MIPTREE_LAYOUT_FOR_BO)
          break;
 
-      mt->tiling = brw_miptree_choose_tiling(brw, requested, mt);
+      mt->tiling = brw_miptree_choose_tiling(brw, mt, layout_flags);
       if (is_tr_mode_yf_ys_allowed) {
          if (intel_miptree_can_use_tr_mode(mt))
             break;