i965: Replace structs with bit-shifting for Gen7 SURFACE_STATE entries.

Every generation except Gen7 creates SURFACE_STATE entries via a
uint32_t array.  Only Gen7 uses the older bitfield structure, which we
moved away from because it was less efficient.  Convert it for
consistency.

This reduces the compiled size of gen7_wm_surface_state.o by 2.86% in a
release build.

v2: Fix accidental use of BRW_SURFACE_WIDTH/HEIGHT in brw_state_dump.c;
    switch back to gen7_set_surface_mcs_info setting surf[6] directly
    (both per Eric's review comments).

Acked-by: Ian Romanick <[email protected]>
Reviewed-by: Eric Anholt <[email protected]>

1 files changed, 0 insertions, 102 deletions

diff --git a/src/mesa/drivers/dri/i965/brw_structs.h b/src/mesa/drivers/dri/i965/brw_structs.h
index a72e9448f24..75365e07566 100644
--- a/src/mesa/drivers/dri/i965/brw_structs.h
+++ b/src/mesa/drivers/dri/i965/brw_structs.h
@@ -774,108 +774,6 @@ struct gen7_sf_clip_viewport {
    GLfloat pad1[4];
 };
 
-/* volume 5c Shared Functions - 1.13.4.1.2 */
-struct gen7_surface_state
-{
-   struct {
-      GLuint cube_pos_z:1;
-      GLuint cube_neg_z:1;
-      GLuint cube_pos_y:1;
-      GLuint cube_neg_y:1;
-      GLuint cube_pos_x:1;
-      GLuint cube_neg_x:1;
-      GLuint pad2:2;
-      GLuint render_cache_read_write:1;
-      GLuint pad1:1;
-      GLuint surface_array_spacing:1;
-      GLuint vert_line_stride_ofs:1;
-      GLuint vert_line_stride:1;
-      GLuint tile_walk:1;
-      GLuint tiled_surface:1;
-      GLuint horizontal_alignment:1;
-      GLuint vertical_alignment:2;
-      GLuint surface_format:9;     /**< BRW_SURFACEFORMAT_x */
-      GLuint pad0:1;
-      GLuint is_array:1;
-      GLuint surface_type:3;       /**< BRW_SURFACE_1D/2D/3D/CUBE */
-   } ss0;
-
-   struct {
-      GLuint base_addr;
-   } ss1;
-
-   struct {
-      GLuint width:14;
-      GLuint pad1:2;
-      GLuint height:14;
-      GLuint pad0:2;
-   } ss2;
-
-   struct {
-      GLuint pitch:18;
-      GLuint pad:3;
-      GLuint depth:11;
-   } ss3;
-
-   struct {
-      GLuint multisample_position_palette_index:3;
-      GLuint num_multisamples:3;
-      GLuint multisampled_surface_storage_format:1;
-      GLuint render_target_view_extent:11;
-      GLuint min_array_elt:11;
-      GLuint rotation:2;
-      GLuint pad0:1;
-   } ss4;
-
-   struct {
-      GLuint mip_count:4;
-      GLuint min_lod:4;
-      GLuint pad1:12;
-      GLuint y_offset:4;
-      GLuint pad0:1;
-      GLuint x_offset:7;
-   } ss5;
-
-   union {
-      GLuint raw_data;
-      struct {
-         GLuint y_offset_for_uv_plane:14;
-         GLuint pad1:2;
-         GLuint x_offset_for_uv_plane:14;
-         GLuint pad0:2;
-      } planar; /** Interpretation when Surface Format == PLANAR */
-      struct {
-         GLuint mcs_enable:1;
-         GLuint append_counter_enable:1;
-         GLuint pad:4;
-         GLuint append_counter_address:26;
-      } mcs_disabled; /** Interpretation when mcs_enable == 0 */
-      struct {
-         GLuint mcs_enable:1;
-         GLuint pad:2;
-         GLuint mcs_surface_pitch:9;
-         GLuint mcs_base_address:20;
-      } mcs_enabled; /** Interpretation when mcs_enable == 1 */
-   } ss6;
-
-   struct {
-      GLuint resource_min_lod:12;
-
-      /* Only on Haswell */
-      GLuint pad0:4;
-      GLuint shader_channel_select_a:3;
-      GLuint shader_channel_select_b:3;
-      GLuint shader_channel_select_g:3;
-      GLuint shader_channel_select_r:3;
-
-      GLuint alpha_clear_color:1;
-      GLuint blue_clear_color:1;
-      GLuint green_clear_color:1;
-      GLuint red_clear_color:1;
-   } ss7;
-};
-
-
 struct brw_vertex_element_state
 {
    struct