i965: Create a macro for setting all dirty bits.

This will make it easier to extend dirty bit handling to support
compute shaders.

Reviewed-by: Jordan Justen <[email protected]>

1 files changed, 3 insertions, 3 deletions

diff --git a/src/mesa/drivers/dri/i965/brw_state_cache.c b/src/mesa/drivers/dri/i965/brw_state_cache.c
index df2d806e7f6..fcb7277bf27 100644
--- a/src/mesa/drivers/dri/i965/brw_state_cache.c
+++ b/src/mesa/drivers/dri/i965/brw_state_cache.c
@@ -379,9 +379,9 @@ brw_clear_cache(struct brw_context *brw, struct brw_cache *cache)
    /* We need to make sure that the programs get regenerated, since
     * any offsets leftover in brw_context will no longer be valid.
     */
-   brw->state.dirty.mesa |= ~0;
-   brw->state.dirty.brw |= ~0;
-   brw->state.dirty.cache |= ~0;
+   SET_DIRTY_ALL(mesa);
+   SET_DIRTY_ALL(brw);
+   SET_DIRTY_ALL(cache);
    intel_batchbuffer_flush(brw);
 }