diff options
| author | Kristian Høgsberg <[email protected]> | 2014-10-20 23:00:50 -0700 |
|---|---|---|
| committer | Kristian Høgsberg <[email protected]> | 2014-12-10 12:29:00 -0800 |
| commit | d9e29f5d88d2ddd8ee9d10b7d88377a60fd0094f (patch) | |
| tree | 0923b33af6ef5b4a0e9e86be33e0f895a162e6b6 /src/mesa/drivers/dri/i965/brw_shader.cpp | |
| parent | 686ef091a4f76fa68d9d9cd5ef00f40c1416a5da (diff) | |
i965: Add SIMD8 URB write low-level IR instruction
This is all we need from the generator for SIMD8 vertex shaders. This
opcode is just the send instruction, all the hard work will happen
in the visitor using LOAD_PAYLOAD.
Signed-off-by: Kristian Høgsberg <[email protected]>
Reviewed-by: Kenneth Graunke <[email protected]>
Diffstat (limited to 'src/mesa/drivers/dri/i965/brw_shader.cpp')
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_shader.cpp | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_shader.cpp b/src/mesa/drivers/dri/i965/brw_shader.cpp index 56aa7578603..b3b1ad79d62 100644 --- a/src/mesa/drivers/dri/i965/brw_shader.cpp +++ b/src/mesa/drivers/dri/i965/brw_shader.cpp @@ -453,6 +453,8 @@ brw_instruction_name(enum opcode op) return "gen4_scratch_write"; case SHADER_OPCODE_GEN7_SCRATCH_READ: return "gen7_scratch_read"; + case SHADER_OPCODE_URB_WRITE_SIMD8: + return "gen8_urb_write_simd8"; case VEC4_OPCODE_PACK_BYTES: return "pack_bytes"; @@ -754,6 +756,7 @@ backend_instruction::has_side_effects() const { switch (opcode) { case SHADER_OPCODE_UNTYPED_ATOMIC: + case SHADER_OPCODE_URB_WRITE_SIMD8: case FS_OPCODE_FB_WRITE: return true; default: |