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authorChris Forbes <[email protected]>2013-06-08 06:11:44 +1200
committerChris Forbes <[email protected]>2013-06-16 01:05:41 +1200
commitdef84d8014e334e00b0a76f7bb635ccc62e3b67e (patch)
tree7bcf496e68de7d611788ca9da7ffd6eaa1b8f6b1 /src/mesa/drivers/dri/i965/brw_sf.h
parent1b77d2133c41c4eb475b81967a3e4d39196c7fe1 (diff)
i965: Shrink Gen5 VUE map layout to be the same as Gen4.
The PRM suggests a larger layout, mostly to support having gl_ClipDistance[] somewhere predictable for the fixed-function clipper -- but it didn't actually arrive in Gen5. Just use the same layout for both Gen4 and Gen5. No Piglit regressions. Improves performance in CS:S Video Stress Test by ~3%. V2: - Remove now-useless function for determining the SF URB read offset - Remove now-unused BRW_VARYING_SLOT_POS_DUPLICATE Signed-off-by: Chris Forbes <[email protected]> Reviewed-by: Paul Berry <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
Diffstat (limited to 'src/mesa/drivers/dri/i965/brw_sf.h')
-rw-r--r--src/mesa/drivers/dri/i965/brw_sf.h3
1 files changed, 2 insertions, 1 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_sf.h b/src/mesa/drivers/dri/i965/brw_sf.h
index f908fc0667b..caeb0d06b1c 100644
--- a/src/mesa/drivers/dri/i965/brw_sf.h
+++ b/src/mesa/drivers/dri/i965/brw_sf.h
@@ -103,6 +103,7 @@ void brw_emit_line_setup( struct brw_sf_compile *c, bool allocate );
void brw_emit_point_setup( struct brw_sf_compile *c, bool allocate );
void brw_emit_point_sprite_setup( struct brw_sf_compile *c, bool allocate );
void brw_emit_anyprim_setup( struct brw_sf_compile *c );
-int brw_sf_compute_urb_entry_read_offset(struct intel_context *intel);
+
+#define BRW_SF_URB_ENTRY_READ_OFFSET 1
#endif