diff options
| author | Kenneth Graunke <[email protected]> | 2012-07-26 11:41:26 -0700 |
|---|---|---|
| committer | Kenneth Graunke <[email protected]> | 2012-08-08 09:23:57 -0700 |
| commit | 61d0b9f52c6be4a4a64c30ea3a2a93ef8260c67b (patch) | |
| tree | 2a3df54a8fdefeae4a523636f58d928bcab5b344 /src/mesa/drivers/dri/i965/brw_queryobj.c | |
| parent | ecac178aa2591afc36e5d34d11a773ff07cb71b1 (diff) | |
intel: Make the length for PIPE_CONTROL explicit.
PIPE_CONTROL has variable length, depending upon generation and whether
we want to do 32-bit or 64-bit data writes. Make it explicit, rather
than hiding a length of 4 in the #define for _3DSTATE_PIPE_CONTROL.
Generated by s/3DSTATE_PIPE_CONTROL/3DSTATE_PIPE_CONTROL | (4 - 2)/g.
This is equivalent since the #define used to have | 2 in it. A grep
through the sources shows that all instances have been converted, so
it's safe to remove the | 2 from the #define.
Signed-off-by: Daniel Vetter <[email protected]>
Signed-off-by: Kenneth Graunke <[email protected]>
Reviewed-by: Daniel Vetter <[email protected]>
Reviewed-by: Eric Anholt <[email protected]>
Diffstat (limited to 'src/mesa/drivers/dri/i965/brw_queryobj.c')
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_queryobj.c | 20 |
1 files changed, 10 insertions, 10 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_queryobj.c b/src/mesa/drivers/dri/i965/brw_queryobj.c index 240fe32bdc5..921fecd9e43 100644 --- a/src/mesa/drivers/dri/i965/brw_queryobj.c +++ b/src/mesa/drivers/dri/i965/brw_queryobj.c @@ -132,7 +132,7 @@ brw_begin_query(struct gl_context *ctx, struct gl_query_object *q) if (intel->gen >= 6) { BEGIN_BATCH(4); - OUT_BATCH(_3DSTATE_PIPE_CONTROL); + OUT_BATCH(_3DSTATE_PIPE_CONTROL | (4 - 2)); OUT_BATCH(PIPE_CONTROL_WRITE_TIMESTAMP); OUT_RELOC(query->bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION, @@ -143,7 +143,7 @@ brw_begin_query(struct gl_context *ctx, struct gl_query_object *q) } else { BEGIN_BATCH(4); - OUT_BATCH(_3DSTATE_PIPE_CONTROL | + OUT_BATCH(_3DSTATE_PIPE_CONTROL | (4 - 2) | PIPE_CONTROL_WRITE_TIMESTAMP); OUT_RELOC(query->bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION, @@ -202,7 +202,7 @@ brw_end_query(struct gl_context *ctx, struct gl_query_object *q) case GL_TIME_ELAPSED_EXT: if (intel->gen >= 6) { BEGIN_BATCH(4); - OUT_BATCH(_3DSTATE_PIPE_CONTROL); + OUT_BATCH(_3DSTATE_PIPE_CONTROL | (4 - 2)); OUT_BATCH(PIPE_CONTROL_WRITE_TIMESTAMP); OUT_RELOC(query->bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION, @@ -213,7 +213,7 @@ brw_end_query(struct gl_context *ctx, struct gl_query_object *q) } else { BEGIN_BATCH(4); - OUT_BATCH(_3DSTATE_PIPE_CONTROL | + OUT_BATCH(_3DSTATE_PIPE_CONTROL | (4 - 2) | PIPE_CONTROL_WRITE_TIMESTAMP); OUT_RELOC(query->bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION, @@ -340,12 +340,12 @@ brw_emit_query_begin(struct brw_context *brw) BEGIN_BATCH(8); /* workaround: CS stall required before depth stall. */ - OUT_BATCH(_3DSTATE_PIPE_CONTROL); + OUT_BATCH(_3DSTATE_PIPE_CONTROL | (4 - 2)); OUT_BATCH(PIPE_CONTROL_CS_STALL); OUT_BATCH(0); /* write address */ OUT_BATCH(0); /* write data */ - OUT_BATCH(_3DSTATE_PIPE_CONTROL); + OUT_BATCH(_3DSTATE_PIPE_CONTROL | (4 - 2)); OUT_BATCH(PIPE_CONTROL_DEPTH_STALL | PIPE_CONTROL_WRITE_DEPTH_COUNT); OUT_RELOC(brw->query.bo, @@ -357,7 +357,7 @@ brw_emit_query_begin(struct brw_context *brw) } else { BEGIN_BATCH(4); - OUT_BATCH(_3DSTATE_PIPE_CONTROL | + OUT_BATCH(_3DSTATE_PIPE_CONTROL | (4 - 2) | PIPE_CONTROL_DEPTH_STALL | PIPE_CONTROL_WRITE_DEPTH_COUNT); /* This object could be mapped cacheable, but we don't have an exposed @@ -397,12 +397,12 @@ brw_emit_query_end(struct brw_context *brw) if (intel->gen >= 6) { BEGIN_BATCH(8); /* workaround: CS stall required before depth stall. */ - OUT_BATCH(_3DSTATE_PIPE_CONTROL); + OUT_BATCH(_3DSTATE_PIPE_CONTROL | (4 - 2)); OUT_BATCH(PIPE_CONTROL_CS_STALL); OUT_BATCH(0); /* write address */ OUT_BATCH(0); /* write data */ - OUT_BATCH(_3DSTATE_PIPE_CONTROL); + OUT_BATCH(_3DSTATE_PIPE_CONTROL | (4 - 2)); OUT_BATCH(PIPE_CONTROL_DEPTH_STALL | PIPE_CONTROL_WRITE_DEPTH_COUNT); OUT_RELOC(brw->query.bo, @@ -414,7 +414,7 @@ brw_emit_query_end(struct brw_context *brw) } else { BEGIN_BATCH(4); - OUT_BATCH(_3DSTATE_PIPE_CONTROL | + OUT_BATCH(_3DSTATE_PIPE_CONTROL | (4 - 2) | PIPE_CONTROL_DEPTH_STALL | PIPE_CONTROL_WRITE_DEPTH_COUNT); OUT_RELOC(brw->query.bo, |