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authorKenneth Graunke <[email protected]>2012-11-20 13:50:52 -0800
committerKenneth Graunke <[email protected]>2012-11-26 19:52:33 -0800
commita303df86de96a428f82377a8c38db8b7e3223447 (patch)
tree4264e019252a9dc99dae0ae7e70d07915aae1ced /src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp
parent47a6a7b51b774091f46aed264b3591fd36c8baed (diff)
i965/fs: Move brw_wm_compile::dispatch_width into fs_visitor.
Also, rather than having brw_wm_fs_emit poke at it directly, make it a parameter to the fs_visitor constructor. All other changes generated by search and replace (with occasional whitespace fixup). v2: Make dispatch_width const (as suggested by Paul); fix doxygen mistake (pointed out by Eric); update for rebase. Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Paul Berry <[email protected]>
Diffstat (limited to 'src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp')
-rw-r--r--src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp10
1 files changed, 5 insertions, 5 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp b/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp
index e83193e24ff..a4fc03218a0 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp
@@ -45,7 +45,7 @@ fs_visitor::assign_regs_trivial()
{
int hw_reg_mapping[this->virtual_grf_count + 1];
int i;
- int reg_width = c->dispatch_width / 8;
+ int reg_width = dispatch_width / 8;
/* Note that compressed instructions require alignment to 2 registers. */
hw_reg_mapping[0] = ALIGN(this->first_non_payload_grf, reg_width);
@@ -216,7 +216,7 @@ fs_visitor::setup_payload_interference(struct ra_graph *g,
int payload_node_count,
int first_payload_node)
{
- int reg_width = c->dispatch_width / 8;
+ int reg_width = dispatch_width / 8;
int loop_depth = 0;
int loop_end_ip = 0;
@@ -338,7 +338,7 @@ void
fs_visitor::setup_mrf_hack_interference(struct ra_graph *g, int first_mrf_node)
{
int mrf_count = BRW_MAX_GRF - GEN7_MRF_HACK_START;
- int reg_width = c->dispatch_width / 8;
+ int reg_width = dispatch_width / 8;
/* Identify all the MRFs used in the program. */
bool mrf_used[mrf_count];
@@ -394,7 +394,7 @@ fs_visitor::assign_regs()
* registers it's allocating be contiguous physical pairs of regs
* for reg_width == 2.
*/
- int reg_width = c->dispatch_width / 8;
+ int reg_width = dispatch_width / 8;
int hw_reg_mapping[this->virtual_grf_count];
int payload_node_count = (ALIGN(this->first_non_payload_grf, reg_width) /
reg_width);
@@ -458,7 +458,7 @@ fs_visitor::assign_regs()
if (reg == -1) {
fail("no register to spill\n");
- } else if (c->dispatch_width == 16) {
+ } else if (dispatch_width == 16) {
fail("Failure to register allocate. Reduce number of live scalar "
"values to avoid this.");
} else {