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author | Kenneth Graunke <[email protected]> | 2015-02-20 14:09:17 -0800 |
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committer | Kenneth Graunke <[email protected]> | 2015-04-06 13:49:02 -0700 |
commit | 8aee87fe4cce0a883867df3546db0e0a36908086 (patch) | |
tree | d9cd7b1bbfca7ae291ebc407485dbc3bf4930678 /src/mesa/drivers/dri/i965/brw_fs.h | |
parent | 108b92b1e9f645e9d2ff33b24648f5d089cb89c9 (diff) |
i965: Use SIMD16 instead of SIMD8 on Gen4 when possible.
Gen5+ systems allow you to specify multiple shader programs - both SIMD8
and SIMD16 - and the hardware will automatically dispatch to the most
appropriate one, given the number of subspans to be processed.
However, that is not the case on Gen4. Instead, you program a single
shader. If you enable multiple dispatch modes (SIMD8 and SIMD16), the
shader is supposed to contain a series of jump instructions at the
beginning. The hardware will launch the shader at a small offset,
hitting one of the jumps.
We've always thought that sounds like a pain, and weren't clear how it
affected performance - is it worth having multiple shader types? So,
we never bothered with SIMD16 until now.
This patch takes a simpler approach: try and compile a SIMD16 shader.
If possible, set the no_8 flag, telling the hardware to just use the
SIMD16 variant all the time.
Signed-off-by: Kenneth Graunke <[email protected]>
Reviewed-by: Jordan Justen <[email protected]>
Diffstat (limited to 'src/mesa/drivers/dri/i965/brw_fs.h')
0 files changed, 0 insertions, 0 deletions