i965: Replace 8-wide and 16-wide with SIMD8 and SIMD16.

Those are the terms used in the docs, and think "n-wide" was something I
just happened to say.  Note that shader-db needs updating for the
INTEL_DEBUG=fs parsing.

Reviewed-by: Ian Romanick <[email protected]>

1 files changed, 4 insertions, 4 deletions

diff --git a/src/mesa/drivers/dri/i965/brw_eu.c b/src/mesa/drivers/dri/i965/brw_eu.c
index 5a07d839730..dee91123ff3 100644
--- a/src/mesa/drivers/dri/i965/brw_eu.c
+++ b/src/mesa/drivers/dri/i965/brw_eu.c
@@ -112,7 +112,7 @@ brw_set_compression_control(struct brw_compile *p,
    p->compressed = (compression_control == BRW_COMPRESSION_COMPRESSED);
 
    if (p->brw->gen >= 6) {
-      /* Since we don't use the 32-wide support in gen6, we translate
+      /* Since we don't use the SIMD32 support in gen6, we translate
        * the pre-gen6 compression control here.
        */
       switch (compression_control) {
@@ -123,12 +123,12 @@ brw_set_compression_control(struct brw_compile *p,
 	 p->current->header.compression_control = GEN6_COMPRESSION_1Q;
 	 break;
       case BRW_COMPRESSION_2NDHALF:
-	 /* For 8-wide, this is "use the second set of 8 bits." */
+	 /* For SIMD8, this is "use the second set of 8 bits." */
 	 p->current->header.compression_control = GEN6_COMPRESSION_2Q;
 	 break;
       case BRW_COMPRESSION_COMPRESSED:
-	 /* For 16-wide instruction compression, use the first set of 16 bits
-	  * since we don't do 32-wide dispatch.
+	 /* For SIMD16 instruction compression, use the first set of 16 bits
+	  * since we don't do SIMD32 dispatch.
 	  */
 	 p->current->header.compression_control = GEN6_COMPRESSION_1H;
 	 break;