diff options
| author | Kristian Høgsberg <[email protected]> | 2014-10-20 23:00:50 -0700 |
|---|---|---|
| committer | Kristian Høgsberg <[email protected]> | 2014-12-10 12:29:00 -0800 |
| commit | d9e29f5d88d2ddd8ee9d10b7d88377a60fd0094f (patch) | |
| tree | 0923b33af6ef5b4a0e9e86be33e0f895a162e6b6 /src/mesa/drivers/dri/i965/brw_defines.h | |
| parent | 686ef091a4f76fa68d9d9cd5ef00f40c1416a5da (diff) | |
i965: Add SIMD8 URB write low-level IR instruction
This is all we need from the generator for SIMD8 vertex shaders. This
opcode is just the send instruction, all the hard work will happen
in the visitor using LOAD_PAYLOAD.
Signed-off-by: Kristian Høgsberg <[email protected]>
Reviewed-by: Kenneth Graunke <[email protected]>
Diffstat (limited to 'src/mesa/drivers/dri/i965/brw_defines.h')
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_defines.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_defines.h b/src/mesa/drivers/dri/i965/brw_defines.h index d4211496168..843ef32cbbd 100644 --- a/src/mesa/drivers/dri/i965/brw_defines.h +++ b/src/mesa/drivers/dri/i965/brw_defines.h @@ -908,6 +908,8 @@ enum opcode { SHADER_OPCODE_GEN4_SCRATCH_WRITE, SHADER_OPCODE_GEN7_SCRATCH_READ, + SHADER_OPCODE_URB_WRITE_SIMD8, + VEC4_OPCODE_PACK_BYTES, VEC4_OPCODE_UNPACK_UNIFORM, @@ -1529,6 +1531,7 @@ enum brw_message_target { #define BRW_URB_OPCODE_WRITE_HWORD 0 #define BRW_URB_OPCODE_WRITE_OWORD 1 +#define GEN8_URB_OPCODE_SIMD8_WRITE 7 #define BRW_URB_SWIZZLE_NONE 0 #define BRW_URB_SWIZZLE_INTERLEAVE 1 |