diff options
| author | Francisco Jerez <[email protected]> | 2015-08-04 19:04:55 +0300 |
|---|---|---|
| committer | Francisco Jerez <[email protected]> | 2015-08-06 14:12:12 +0300 |
| commit | 8f5d0988ea2ccaba7f049f113b652f331524d2a6 (patch) | |
| tree | c86698766eec7f268fc40a8eff912c966783f0b0 /src/mesa/drivers/dri/i965/brw_defines.h | |
| parent | f7ac4ef4eeea737115d0b574fed7ecae46426072 (diff) | |
i965: Define virtual instruction to calculate the high 32 bits of a multiply.
This instruction will translate to the MUL/MACH sequence that computes
the high 32-bits of the result of a 64-bit multiply. Before Gen8
integer operations that used the accumulator were limited to 8-wide,
but the SIMD lowering pass can easily be hooked up to sidestep this
limitation, we just need a virtual opcode to represent the MUL/MACH
sequence in the IR.
Reviewed-by: Matt Turner <[email protected]>
Diffstat (limited to 'src/mesa/drivers/dri/i965/brw_defines.h')
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_defines.h | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_defines.h b/src/mesa/drivers/dri/i965/brw_defines.h index f595366eeac..9c232c46ff3 100644 --- a/src/mesa/drivers/dri/i965/brw_defines.h +++ b/src/mesa/drivers/dri/i965/brw_defines.h @@ -1214,6 +1214,11 @@ enum opcode { * GLSL barrier() */ SHADER_OPCODE_BARRIER, + + /** + * Calculate the high 32-bits of a 32x32 multiply. + */ + SHADER_OPCODE_MULH, }; enum brw_urb_write_flags { |