diff options
| author | Kenneth Graunke <[email protected]> | 2012-12-28 12:45:14 -0800 |
|---|---|---|
| committer | Kenneth Graunke <[email protected]> | 2013-01-03 13:36:04 -0800 |
| commit | 82f8e8ebd57720f1e9d148c7dc65b14c218307df (patch) | |
| tree | 5b27bf47cbab91f7ce66779b2f11f59e388a0a7d /src/mesa/drivers/dri/i965/brw_defines.h | |
| parent | 5bf357db89836d0f4e4b8a4cb559755d4734b81b (diff) | |
i965: Replace structs with bit-shifting for Gen7 SURFACE_STATE entries.
Every generation except Gen7 creates SURFACE_STATE entries via a
uint32_t array. Only Gen7 uses the older bitfield structure, which we
moved away from because it was less efficient. Convert it for
consistency.
This reduces the compiled size of gen7_wm_surface_state.o by 2.86% in a
release build.
v2: Fix accidental use of BRW_SURFACE_WIDTH/HEIGHT in brw_state_dump.c;
switch back to gen7_set_surface_mcs_info setting surf[6] directly
(both per Eric's review comments).
Acked-by: Ian Romanick <[email protected]>
Reviewed-by: Eric Anholt <[email protected]>
Diffstat (limited to 'src/mesa/drivers/dri/i965/brw_defines.h')
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_defines.h | 43 |
1 files changed, 36 insertions, 7 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_defines.h b/src/mesa/drivers/dri/i965/brw_defines.h index ab206d1920f..1d0cf0275d1 100644 --- a/src/mesa/drivers/dri/i965/brw_defines.h +++ b/src/mesa/drivers/dri/i965/brw_defines.h @@ -439,8 +439,16 @@ #define BRW_SURFACE_BUFFER 4 #define BRW_SURFACE_NULL 7 -#define GEN7_SURFACE_ARYSPC_FULL 0 -#define GEN7_SURFACE_ARYSPC_LOD0 1 +#define GEN7_SURFACE_IS_ARRAY (1 << 28) +#define GEN7_SURFACE_VALIGN_2 (0 << 16) +#define GEN7_SURFACE_VALIGN_4 (1 << 16) +#define GEN7_SURFACE_HALIGN_4 (0 << 15) +#define GEN7_SURFACE_HALIGN_8 (1 << 15) +#define GEN7_SURFACE_TILING_NONE (0 << 13) +#define GEN7_SURFACE_TILING_X (2 << 13) +#define GEN7_SURFACE_TILING_Y (3 << 13) +#define GEN7_SURFACE_ARYSPC_FULL (0 << 10) +#define GEN7_SURFACE_ARYSPC_LOD0 (1 << 10) /* Surface state DW2 */ #define BRW_SURFACE_HEIGHT_SHIFT 19 @@ -449,6 +457,10 @@ #define BRW_SURFACE_WIDTH_MASK INTEL_MASK(18, 6) #define BRW_SURFACE_LOD_SHIFT 2 #define BRW_SURFACE_LOD_MASK INTEL_MASK(5, 2) +#define GEN7_SURFACE_HEIGHT_SHIFT 16 +#define GEN7_SURFACE_HEIGHT_MASK INTEL_MASK(29, 16) +#define GEN7_SURFACE_WIDTH_SHIFT 0 +#define GEN7_SURFACE_WIDTH_MASK INTEL_MASK(13, 0) /* Surface state DW3 */ #define BRW_SURFACE_DEPTH_SHIFT 21 @@ -463,11 +475,11 @@ #define BRW_SURFACE_MIN_LOD_MASK INTEL_MASK(31, 28) #define BRW_SURFACE_MULTISAMPLECOUNT_1 (0 << 4) #define BRW_SURFACE_MULTISAMPLECOUNT_4 (2 << 4) -#define GEN7_SURFACE_MULTISAMPLECOUNT_1 0 -#define GEN7_SURFACE_MULTISAMPLECOUNT_4 2 -#define GEN7_SURFACE_MULTISAMPLECOUNT_8 3 -#define GEN7_SURFACE_MSFMT_MSS 0 -#define GEN7_SURFACE_MSFMT_DEPTH_STENCIL 1 +#define GEN7_SURFACE_MULTISAMPLECOUNT_1 (0 << 3) +#define GEN7_SURFACE_MULTISAMPLECOUNT_4 (2 << 3) +#define GEN7_SURFACE_MULTISAMPLECOUNT_8 (3 << 3) +#define GEN7_SURFACE_MSFMT_MSS (0 << 6) +#define GEN7_SURFACE_MSFMT_DEPTH_STENCIL (1 << 6) /* Surface state DW5 */ #define BRW_SURFACE_X_OFFSET_SHIFT 25 @@ -475,8 +487,25 @@ #define BRW_SURFACE_VERTICAL_ALIGN_ENABLE (1 << 24) #define BRW_SURFACE_Y_OFFSET_SHIFT 20 #define BRW_SURFACE_Y_OFFSET_MASK INTEL_MASK(23, 20) +#define GEN7_SURFACE_MIN_LOD_SHIFT 4 +#define GEN7_SURFACE_MIN_LOD_MASK INTEL_MASK(7, 4) + +/* Surface state DW6 */ +#define GEN7_SURFACE_MCS_ENABLE (1 << 0) +#define GEN7_SURFACE_MCS_PITCH_SHIFT 3 +#define GEN7_SURFACE_MCS_PITCH_MASK INTEL_MASK(11, 3) /* Surface state DW7 */ +#define GEN7_SURFACE_SCS_R_SHIFT 25 +#define GEN7_SURFACE_SCS_R_MASK INTEL_MASK(27, 25) +#define GEN7_SURFACE_SCS_G_SHIFT 22 +#define GEN7_SURFACE_SCS_G_MASK INTEL_MASK(24, 22) +#define GEN7_SURFACE_SCS_B_SHIFT 19 +#define GEN7_SURFACE_SCS_B_MASK INTEL_MASK(21, 19) +#define GEN7_SURFACE_SCS_A_SHIFT 16 +#define GEN7_SURFACE_SCS_A_MASK INTEL_MASK(18, 16) + +/* The actual swizzle values/what channel to use */ #define HSW_SCS_ZERO 0 #define HSW_SCS_ONE 1 #define HSW_SCS_RED 4 |