summaryrefslogtreecommitdiffstats
path: root/src/mesa/drivers/dri/i965/brw_defines.h
diff options
context:
space:
mode:
authorKenneth Graunke <kenneth@whitecape.org>2013-11-04 23:19:55 -0800
committerKenneth Graunke <kenneth@whitecape.org>2014-01-31 17:50:08 -0800
commit4c4e0ed64bceca57e19c0a9f53aae77d795aa937 (patch)
tree50c6927258e4983f99ee5457ad4d4b27c79a2dc7 /src/mesa/drivers/dri/i965/brw_defines.h
parenta0d4311072267aa5427eb2cacd820e96f114eba0 (diff)
i965: Update GS state for Broadwell.
This is quite similar to the Gen7 code. The main changes: - 48-bit relocations - Thread count is specified as U/2-1 instead of U-1. - An extra DWord (DW9) with clip planes, URB entry output length/offsets - We need to program the "Expected Vertex Count" (VerticesIn) v2: Set the number of binding table entries so they can be prefetched (requested by Eric Anholt). v3: Add a WARN_ONCE for a missing workaround. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
Diffstat (limited to 'src/mesa/drivers/dri/i965/brw_defines.h')
-rw-r--r--src/mesa/drivers/dri/i965/brw_defines.h5
1 files changed, 5 insertions, 0 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_defines.h b/src/mesa/drivers/dri/i965/brw_defines.h
index e2869422f2a..b29d0c44bb8 100644
--- a/src/mesa/drivers/dri/i965/brw_defines.h
+++ b/src/mesa/drivers/dri/i965/brw_defines.h
@@ -1530,6 +1530,11 @@ enum brw_message_target {
# define GEN6_GS_SVBI_POSTINCREMENT_VALUE_MASK INTEL_MASK(25, 16)
# define GEN6_GS_ENABLE (1 << 15)
+/* Gen8+ DW9 */
+# define GEN8_GS_URB_ENTRY_OUTPUT_OFFSET_SHIFT 21
+# define GEN8_GS_URB_OUTPUT_LENGTH_SHIFT 16
+# define GEN8_GS_USER_CLIP_DISTANCE_SHIFT 8
+
# define BRW_GS_EDGE_INDICATOR_0 (1 << 8)
# define BRW_GS_EDGE_INDICATOR_1 (1 << 9)