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authorKenneth Graunke <[email protected]>2014-10-22 08:58:58 -0700
committerKenneth Graunke <[email protected]>2014-11-04 11:38:01 -0800
commit7423cc891b4d6fcc63bfeb79cc1d711ce81122bd (patch)
treed303842e3932b852d6b4351f685545fa5b928ca9 /src/mesa/drivers/dri/i965/brw_context.h
parent8ccf54ab098032da4652b314761c04f7724a7277 (diff)
i965: Implement the PMA stall fix.
Certain non-promoted depth cases typically incur stalls. In very specific cases, we can enable a workaround which improves performance. Improves performance in GLBenchmark 2.7 TRex by 1.17762% +/- 0.448765% (n=75) at 1280x720 on Broadwell GT3. Haswell has this feature as well, but we can't currently write registers from userspace batches (and we'd incur additional software batch scanning overhead as well), so we haven't enabled it. Broadwell allows us to write CACHE_MODE_1. Backporters beware: the formula and flushing incantation differs between Haswell and Broadwell. v2: Move pma_stall_bits from brw->state to brw itself (requested by Kristian Høgsberg). Signed-off-by: Kenneth Graunke <[email protected]>
Diffstat (limited to 'src/mesa/drivers/dri/i965/brw_context.h')
-rw-r--r--src/mesa/drivers/dri/i965/brw_context.h3
1 files changed, 3 insertions, 0 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_context.h b/src/mesa/drivers/dri/i965/brw_context.h
index eb37e750f6d..656cbe8ce84 100644
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -1092,6 +1092,9 @@ struct brw_context
/* Whether the last depth/stencil packets were both NULL. */
bool no_depth_or_stencil;
+ /* The last PMA stall bits programmed. */
+ uint32_t pma_stall_bits;
+
struct {
/** Does the current draw use the index buffer? */
bool indexed;