i965/vs: Replace brw_vs_emit.c with dumping code into the vec4_visitor.

Rather than having two separate backends, just create a small layer that
translates the subset of Mesa IR used for ARB_vertex_program and fixed
function programs to the Vec4 IR.  This allows us to use the same
optimization passes, code generator, register allocator as for GLSL.

v2: Incorporate Eric's review comments.
- Fix use of uninitialized src_swiz[] values in the SWIZZLE_ZERO/ONE
  case: just initialize it to 0 (.x) since the value doesn't matter
  (those channels get writemasked out anyway).
- Properly reswizzle source register's swizzles, rather than overwriting
  the swizzle.
- Port the old brw_vs_emit code for computing .x of the EXP2 opcode.
- Update comments, removing mention of NV_vertex_program, etc.
- Delete remaining #warning lines and debug comments.

Signed-off-by: Kenneth Graunke <[email protected]>
Reviewed-by: Eric Anholt <[email protected]>

1 files changed, 1 insertions, 0 deletions

diff --git a/src/mesa/drivers/dri/i965/Makefile.sources b/src/mesa/drivers/dri/i965/Makefile.sources
index c0a42124641..dc65908a8d4 100644
--- a/src/mesa/drivers/dri/i965/Makefile.sources
+++ b/src/mesa/drivers/dri/i965/Makefile.sources
@@ -128,6 +128,7 @@ i965_CXX_FILES = \
 	brw_vec4_live_variables.cpp \
 	brw_vec4_reg_allocate.cpp \
 	brw_vec4_visitor.cpp \
+	brw_vec4_vp.cpp \
 	gen6_blorp.cpp \
 	gen7_blorp.cpp