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authorIan Romanick <ian.d.romanick@intel.com>2017-06-02 17:29:53 -0700
committerIan Romanick <ian.d.romanick@intel.com>2017-06-26 15:20:09 -0700
commit122e6dc45112e1627da11161b488d89e29730c81 (patch)
tree0d6efa4307b8cd6b2b9cda9df1b4a46c535d629c /src/mesa/drivers/dri/i915
parent97d332ce0e9e47714da20f799e6f1a92fb1f53dd (diff)
i915: On Gen <= 3 there is no W-tiling
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Diffstat (limited to 'src/mesa/drivers/dri/i915')
-rw-r--r--src/mesa/drivers/dri/i915/intel_mipmap_tree.c5
-rw-r--r--src/mesa/drivers/dri/i915/intel_regions.c21
-rw-r--r--src/mesa/drivers/dri/i915/intel_regions.h5
-rw-r--r--src/mesa/drivers/dri/i915/intel_screen.c7
4 files changed, 9 insertions, 29 deletions
diff --git a/src/mesa/drivers/dri/i915/intel_mipmap_tree.c b/src/mesa/drivers/dri/i915/intel_mipmap_tree.c
index 6c0f55b6389..bb6166e01ab 100644
--- a/src/mesa/drivers/dri/i915/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i915/intel_mipmap_tree.c
@@ -525,14 +525,13 @@ intel_miptree_get_tile_offsets(struct intel_mipmap_tree *mt,
uint32_t x, y;
uint32_t mask_x, mask_y;
- intel_region_get_tile_masks(region, &mask_x, &mask_y, false);
+ intel_region_get_tile_masks(region, &mask_x, &mask_y);
intel_miptree_get_image_offset(mt, level, slice, &x, &y);
*tile_x = x & mask_x;
*tile_y = y & mask_y;
- return intel_region_get_aligned_offset(region, x & ~mask_x, y & ~mask_y,
- false);
+ return intel_region_get_aligned_offset(region, x & ~mask_x, y & ~mask_y);
}
static void
diff --git a/src/mesa/drivers/dri/i915/intel_regions.c b/src/mesa/drivers/dri/i915/intel_regions.c
index c9b776d1a0f..be0dca497e8 100644
--- a/src/mesa/drivers/dri/i915/intel_regions.c
+++ b/src/mesa/drivers/dri/i915/intel_regions.c
@@ -284,15 +284,11 @@ intel_region_release(struct intel_region **region_handle)
*/
void
intel_region_get_tile_masks(struct intel_region *region,
- uint32_t *mask_x, uint32_t *mask_y,
- bool map_stencil_as_y_tiled)
+ uint32_t *mask_x, uint32_t *mask_y)
{
int cpp = region->cpp;
uint32_t tiling = region->tiling;
- if (map_stencil_as_y_tiled)
- tiling = I915_TILING_Y;
-
switch (tiling) {
default:
assert(false);
@@ -317,25 +313,12 @@ intel_region_get_tile_masks(struct intel_region *region,
*/
uint32_t
intel_region_get_aligned_offset(struct intel_region *region, uint32_t x,
- uint32_t y, bool map_stencil_as_y_tiled)
+ uint32_t y)
{
int cpp = region->cpp;
uint32_t pitch = region->pitch;
uint32_t tiling = region->tiling;
- if (map_stencil_as_y_tiled) {
- tiling = I915_TILING_Y;
-
- /* When mapping a W-tiled stencil buffer as Y-tiled, each 64-high W-tile
- * gets transformed into a 32-high Y-tile. Accordingly, the pitch of
- * the resulting region is twice the pitch of the original region, since
- * each row in the Y-tiled view corresponds to two rows in the actual
- * W-tiled surface. So we need to correct the pitch before computing
- * the offsets.
- */
- pitch *= 2;
- }
-
switch (tiling) {
default:
assert(false);
diff --git a/src/mesa/drivers/dri/i915/intel_regions.h b/src/mesa/drivers/dri/i915/intel_regions.h
index 562f7cd902b..05375f1c41e 100644
--- a/src/mesa/drivers/dri/i915/intel_regions.h
+++ b/src/mesa/drivers/dri/i915/intel_regions.h
@@ -101,12 +101,11 @@ void intel_recreate_static_regions(struct intel_context *intel);
void
intel_region_get_tile_masks(struct intel_region *region,
- uint32_t *mask_x, uint32_t *mask_y,
- bool map_stencil_as_y_tiled);
+ uint32_t *mask_x, uint32_t *mask_y);
uint32_t
intel_region_get_aligned_offset(struct intel_region *region, uint32_t x,
- uint32_t y, bool map_stencil_as_y_tiled);
+ uint32_t y);
/**
* Used with images created with image_from_names
diff --git a/src/mesa/drivers/dri/i915/intel_screen.c b/src/mesa/drivers/dri/i915/intel_screen.c
index cba5434b5e1..fe8ece78fca 100644
--- a/src/mesa/drivers/dri/i915/intel_screen.c
+++ b/src/mesa/drivers/dri/i915/intel_screen.c
@@ -278,7 +278,7 @@ intel_setup_image_from_mipmap_tree(struct intel_context *intel, __DRIimage *imag
intel_miptree_check_level_layer(mt, level, zoffset);
- intel_region_get_tile_masks(mt->region, &mask_x, &mask_y, false);
+ intel_region_get_tile_masks(mt->region, &mask_x, &mask_y);
intel_miptree_get_image_offset(mt, level, zoffset, &draw_x, &draw_y);
image->width = mt->level[level].width;
@@ -288,8 +288,7 @@ intel_setup_image_from_mipmap_tree(struct intel_context *intel, __DRIimage *imag
image->offset = intel_region_get_aligned_offset(mt->region,
draw_x & ~mask_x,
- draw_y & ~mask_y,
- false);
+ draw_y & ~mask_y);
intel_region_reference(&image->region, mt->region);
}
@@ -685,7 +684,7 @@ intel_from_planar(__DRIimage *parent, int plane, void *loaderPrivate)
image->offset = offset;
intel_setup_image_from_dimensions(image);
- intel_region_get_tile_masks(image->region, &mask_x, &mask_y, false);
+ intel_region_get_tile_masks(image->region, &mask_x, &mask_y);
if (offset & mask_x)
_mesa_warning(NULL,
"intel_create_sub_image: offset not on tile boundary");