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authorEric Anholt <[email protected]>2008-02-13 10:34:20 -0800
committerEric Anholt <[email protected]>2008-02-13 10:38:05 -0800
commit822b2481ffc0d3e2ca9d24e9443634af2760777c (patch)
treef0ebda395782a8b44ffc8cb9d5527e59e4d16968 /src/mesa/drivers/dri/i915
parentee781a41af95a317f4f37182e0d614e917e0737d (diff)
[intel] Fix 965 rendering with non-TTM by merging intel_ioctl between 915/965.
The 965 path wasn't setting pClipRects for batch submission since it didn't want kernel cliprect handling before. The 915 path also grew the INTEL_NO_HW=1 option for testing just driver overhead.
Diffstat (limited to 'src/mesa/drivers/dri/i915')
-rw-r--r--src/mesa/drivers/dri/i915/intel_context.c5
-rw-r--r--src/mesa/drivers/dri/i915/intel_context.h2
l---------[-rw-r--r--]src/mesa/drivers/dri/i915/intel_ioctl.c175
3 files changed, 8 insertions, 174 deletions
diff --git a/src/mesa/drivers/dri/i915/intel_context.c b/src/mesa/drivers/dri/i915/intel_context.c
index 21da8af0404..b2d9c9c5918 100644
--- a/src/mesa/drivers/dri/i915/intel_context.c
+++ b/src/mesa/drivers/dri/i915/intel_context.c
@@ -553,6 +553,11 @@ intelInitContext(struct intel_context *intel,
FALLBACK(intel, INTEL_FALLBACK_USER, 1);
}
+ /* Disable all hardware rendering (skip emitting batches and fences/waits
+ * to the kernel)
+ */
+ intel->no_hw = getenv("INTEL_NO_HW") != NULL;
+
return GL_TRUE;
}
diff --git a/src/mesa/drivers/dri/i915/intel_context.h b/src/mesa/drivers/dri/i915/intel_context.h
index be78b475b4f..151e9e276d2 100644
--- a/src/mesa/drivers/dri/i915/intel_context.h
+++ b/src/mesa/drivers/dri/i915/intel_context.h
@@ -240,6 +240,8 @@ struct intel_context
GLuint lastStamp;
+ GLboolean no_hw;
+
/**
* Configuration cache
*/
diff --git a/src/mesa/drivers/dri/i915/intel_ioctl.c b/src/mesa/drivers/dri/i915/intel_ioctl.c
index 187a6e901b1..effd0f378d2 100644..120000
--- a/src/mesa/drivers/dri/i915/intel_ioctl.c
+++ b/src/mesa/drivers/dri/i915/intel_ioctl.c
@@ -1,174 +1 @@
-/**************************************************************************
- *
- * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
- * All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the
- * "Software"), to deal in the Software without restriction, including
- * without limitation the rights to use, copy, modify, merge, publish,
- * distribute, sub license, and/or sell copies of the Software, and to
- * permit persons to whom the Software is furnished to do so, subject to
- * the following conditions:
- *
- * The above copyright notice and this permission notice (including the
- * next paragraph) shall be included in all copies or substantial portions
- * of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
- * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
- * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
- * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
- * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
- * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- **************************************************************************/
-
-
-#include <stdio.h>
-#include <unistd.h>
-#include <errno.h>
-#include <sched.h>
-
-#include "mtypes.h"
-#include "context.h"
-#include "swrast/swrast.h"
-
-#include "intel_context.h"
-#include "intel_ioctl.h"
-#include "intel_batchbuffer.h"
-#include "intel_blit.h"
-#include "intel_regions.h"
-#include "drm.h"
-
-#include "intel_bufmgr_ttm.h"
-
-#define FILE_DEBUG_FLAG DEBUG_IOCTL
-
-int
-intelEmitIrqLocked(struct intel_context *intel)
-{
- drmI830IrqEmit ie;
- int ret, seq;
-
- ie.irq_seq = &seq;
-
- ret = drmCommandWriteRead(intel->driFd, DRM_I830_IRQ_EMIT, &ie, sizeof(ie));
- if (ret) {
- fprintf(stderr, "%s: drmI830IrqEmit: %d\n", __FUNCTION__, ret);
- exit(1);
- }
-
- DBG("%s --> %d\n", __FUNCTION__, seq);
-
- return seq;
-}
-
-void
-intelWaitIrq(struct intel_context *intel, int seq)
-{
- drm_i915_irq_wait_t iw;
- int ret;
-
- DBG("%s %d\n", __FUNCTION__, seq);
-
- iw.irq_seq = seq;
-
- do {
- ret = drmCommandWrite(intel->driFd, DRM_I830_IRQ_WAIT, &iw, sizeof(iw));
- } while (ret == -EAGAIN || ret == -EINTR);
-
- if (ret) {
- fprintf(stderr, "%s: drmI830IrqWait: %d\n", __FUNCTION__, ret);
- exit(1);
- }
-}
-
-
-void
-intel_batch_ioctl(struct intel_context *intel,
- GLuint start_offset,
- GLuint used,
- GLboolean ignore_cliprects, GLboolean allow_unlock)
-{
- drmI830BatchBuffer batch;
-
- assert(intel->locked);
- assert(used);
-
- DBG("%s used %d offset %x..%x ignore_cliprects %d\n",
- __FUNCTION__,
- used, start_offset, start_offset + used, ignore_cliprects);
-
- /* Throw away non-effective packets. Won't work once we have
- * hardware contexts which would preserve statechanges beyond a
- * single buffer.
- */
- batch.start = start_offset;
- batch.used = used;
- batch.cliprects = intel->pClipRects;
- batch.num_cliprects = ignore_cliprects ? 0 : intel->numClipRects;
- batch.DR1 = 0;
- batch.DR4 = ((((GLuint) intel->drawX) & 0xffff) |
- (((GLuint) intel->drawY) << 16));
-
- DBG("%s: 0x%x..0x%x DR4: %x cliprects: %d\n",
- __FUNCTION__,
- batch.start,
- batch.start + batch.used * 4, batch.DR4, batch.num_cliprects);
-
- if (drmCommandWrite(intel->driFd, DRM_I830_BATCHBUFFER, &batch,
- sizeof(batch))) {
- fprintf(stderr, "DRM_I830_BATCHBUFFER: %d\n", -errno);
- UNLOCK_HARDWARE(intel);
- exit(1);
- }
-}
-
-void
-intel_exec_ioctl(struct intel_context *intel,
- GLuint used,
- GLboolean ignore_cliprects, GLboolean allow_unlock,
- void *start, GLuint count, dri_fence **fence)
-{
- struct drm_i915_execbuffer execbuf;
- dri_fence *fo;
-
- assert(intel->locked);
- assert(used);
-
- if (*fence) {
- dri_fence_unreference(*fence);
- }
-
- memset(&execbuf, 0, sizeof(execbuf));
-
- execbuf.num_buffers = count;
- execbuf.batch.used = used;
- execbuf.batch.cliprects = intel->pClipRects;
- execbuf.batch.num_cliprects = ignore_cliprects ? 0 : intel->numClipRects;
- execbuf.batch.DR1 = 0;
- execbuf.batch.DR4 = ((((GLuint) intel->drawX) & 0xffff) |
- (((GLuint) intel->drawY) << 16));
-
- execbuf.ops_list = (unsigned long)start; // TODO
- execbuf.fence_arg.flags = DRM_FENCE_FLAG_SHAREABLE | DRM_I915_FENCE_FLAG_FLUSHED;
-
- if (drmCommandWriteRead(intel->driFd, DRM_I915_EXECBUFFER, &execbuf,
- sizeof(execbuf))) {
- fprintf(stderr, "DRM_I830_EXECBUFFER: %d\n", -errno);
- UNLOCK_HARDWARE(intel);
- exit(1);
- }
-
-
- fo = intel_ttm_fence_create_from_arg(intel->bufmgr, "fence buffers",
- &execbuf.fence_arg);
- if (!fo) {
- fprintf(stderr, "failed to fence handle: %08x\n", execbuf.fence_arg.handle);
- UNLOCK_HARDWARE(intel);
- exit(1);
- }
- *fence = fo;
-}
+../intel/intel_ioctl.c \ No newline at end of file