Revert "Merge branch 'drm-gem'"

This reverts commit 53675e5c05c0598b7ea206d5c27dbcae786a2c03.

Conflicts:

	src/mesa/drivers/dri/i965/brw_wm_surface_state.c

12 files changed, 261 insertions, 224 deletions

diff --git a/src/mesa/drivers/dri/i915/Makefile b/src/mesa/drivers/dri/i915/Makefile
index fd77980ebf8..bdd3b852603 100644
--- a/src/mesa/drivers/dri/i915/Makefile
+++ b/src/mesa/drivers/dri/i915/Makefile
@@ -30,8 +30,8 @@ DRIVER_SOURCES = \
 	intel_pixel.c \
 	intel_pixel_bitmap.c \
 	intel_pixel_copy.c \
-	intel_pixel_draw.c \
 	intel_pixel_read.c \
+	intel_pixel_draw.c \
 	intel_buffers.c \
 	intel_blit.c \
 	i915_tex.c \
@@ -52,10 +52,12 @@ DRIVER_SOURCES = \
 	intel_state.c \
 	intel_tris.c \
 	intel_fbo.c \
-	intel_depthstencil.c
+	intel_depthstencil.c \
+	intel_bufmgr_ttm.c
 
 C_SOURCES = \
 	$(COMMON_SOURCES) \
+	$(COMMON_BM_SOURCES) \
 	$(DRIVER_SOURCES)
 
 ASM_SOURCES = 
@@ -67,7 +69,6 @@ DRIVER_DEFINES = -I../intel -I../intel/server -DI915 \
 include ../Makefile.template
 
 intel_decode.o: ../intel/intel_decode.c
-
 intel_tex_layout.o: ../intel/intel_tex_layout.c
 
 symlinks:
diff --git a/src/mesa/drivers/dri/i915/i830_context.c b/src/mesa/drivers/dri/i915/i830_context.c
index 116b52511f5..16c8a8d24f1 100644
--- a/src/mesa/drivers/dri/i915/i830_context.c
+++ b/src/mesa/drivers/dri/i915/i830_context.c
@@ -81,9 +81,6 @@ i830CreateContext(const __GLcontextModes * mesaVis,
    _tnl_destroy_pipeline(ctx);
    _tnl_install_pipeline(ctx, intel_pipeline);
 
-   if (intel->no_rast)
-      FALLBACK(intel, INTEL_FALLBACK_USER, 1);
-
    intel->ctx.Const.MaxTextureUnits = I830_TEX_UNITS;
    intel->ctx.Const.MaxTextureImageUnits = I830_TEX_UNITS;
    intel->ctx.Const.MaxTextureCoordUnits = I830_TEX_UNITS;
diff --git a/src/mesa/drivers/dri/i915/i830_reg.h b/src/mesa/drivers/dri/i915/i830_reg.h
index d210c2d08e4..41280bca7ce 100644
--- a/src/mesa/drivers/dri/i915/i830_reg.h
+++ b/src/mesa/drivers/dri/i915/i830_reg.h
@@ -494,6 +494,10 @@
 #define VFT1_TEX0_FMT(x)	(x)
 #define VFT1_TEX0_MASK          3
 #define VFT1_TEX1_SHIFT         2
+#define TEXCOORDFMT_2D		0
+#define TEXCOORDFMT_3D		1
+#define TEXCOORDFMT_4D		2
+#define TEXCOORDFMT_1D		3
 
 /*New stuff picked up along the way */
 
@@ -631,4 +635,8 @@
 #define ENABLE_TEX_STREAM_MAP_IDX	(1<<3)
 #define TEX_STREAM_MAP_IDX(x)		(x)
 
+
+#define MI_FLUSH           ((0<<29)|(4<<23))
+#define FLUSH_MAP_CACHE    (1<<0)
+
 #endif
diff --git a/src/mesa/drivers/dri/i915/i830_vtbl.c b/src/mesa/drivers/dri/i915/i830_vtbl.c
index 40a50ff772f..c5a85fe0352 100644
--- a/src/mesa/drivers/dri/i915/i830_vtbl.c
+++ b/src/mesa/drivers/dri/i915/i830_vtbl.c
@@ -31,7 +31,6 @@
 #include "i830_reg.h"
 #include "intel_batchbuffer.h"
 #include "intel_regions.h"
-#include "intel_tris.h"
 #include "tnl/t_context.h"
 #include "tnl/t_vertex.h"
 
@@ -420,12 +419,10 @@ i830_emit_state(struct intel_context *intel)
 {
    struct i830_context *i830 = i830_context(&intel->ctx);
    struct i830_hw_state *state = i830->current;
-   int i, count;
+   int i, ret, count;
    GLuint dirty;
    GET_CURRENT_CONTEXT(ctx);
    BATCH_LOCALS;
-   dri_bo *aper_array[3 + I830_TEX_UNITS];
-   int aper_count;
 
    /* We don't hold the lock at this point, so want to make sure that
     * there won't be a buffer wrap between the state emits and the primitive
@@ -438,28 +435,26 @@ i830_emit_state(struct intel_context *intel)
     * Set the space as LOOP_CLIPRECTS now, since that's what our primitives
     * will be emitted under.
     */
-   intel_batchbuffer_require_space(intel->batch,
-				   get_state_size(state) + INTEL_PRIM_EMIT_SIZE,
+   intel_batchbuffer_require_space(intel->batch, get_state_size(state) + 8,
 				   LOOP_CLIPRECTS);
    count = 0;
  again:
-   aper_count = 0;
    dirty = get_dirty(state);
 
-   aper_array[aper_count++] = intel->batch->buf;
+   ret = 0;
    if (dirty & I830_UPLOAD_BUFFERS) {
-      aper_array[aper_count++] = state->draw_region->buffer;
-      aper_array[aper_count++] = state->depth_region->buffer;
+     ret |= dri_bufmgr_check_aperture_space(state->draw_region->buffer);
+     ret |= dri_bufmgr_check_aperture_space(state->depth_region->buffer);
    }
-
+   
    for (i = 0; i < I830_TEX_UNITS; i++)
      if (dirty & I830_UPLOAD_TEX(i)) {
 	if (state->tex_buffer[i]) {
-	   aper_array[aper_count++] = state->tex_buffer[i];
+	  ret |= dri_bufmgr_check_aperture_space(state->tex_buffer[i]);
 	}
      }
 
-   if (dri_bufmgr_check_aperture_space(aper_array, aper_count)) {
+   if (ret) {
        if (count == 0) {
 	   count++;
 	   intel_batchbuffer_flush(intel->batch);
@@ -495,14 +490,14 @@ i830_emit_state(struct intel_context *intel)
       OUT_BATCH(state->Buffer[I830_DESTREG_CBUFADDR0]);
       OUT_BATCH(state->Buffer[I830_DESTREG_CBUFADDR1]);
       OUT_RELOC(state->draw_region->buffer,
-		I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
+                DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_WRITE,
                 state->draw_region->draw_offset);
 
       if (state->depth_region) {
          OUT_BATCH(state->Buffer[I830_DESTREG_DBUFADDR0]);
          OUT_BATCH(state->Buffer[I830_DESTREG_DBUFADDR1]);
          OUT_RELOC(state->depth_region->buffer,
-		   I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
+                   DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_WRITE,
                    state->depth_region->draw_offset);
       }
 
@@ -529,7 +524,7 @@ i830_emit_state(struct intel_context *intel)
 
          if (state->tex_buffer[i]) {
             OUT_RELOC(state->tex_buffer[i],
-		      I915_GEM_DOMAIN_SAMPLER, 0,
+                      DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_READ,
                       state->tex_offset[i] | TM0S0_USE_FENCE);
          }
 	 else if (state == &i830->meta) {
@@ -722,5 +717,4 @@ i830InitVtbl(struct i830_context *i830)
    i830->intel.vtbl.render_prevalidate = i830_render_prevalidate;
    i830->intel.vtbl.assert_not_dirty = i830_assert_not_dirty;
    i830->intel.vtbl.note_unlock = i830_note_unlock; 
-   i830->intel.vtbl.finish_batch = intel_finish_vb;
 }
diff --git a/src/mesa/drivers/dri/i915/i915_context.c b/src/mesa/drivers/dri/i915/i915_context.c
index 940b02513da..bd9f1d5f5dc 100644
--- a/src/mesa/drivers/dri/i915/i915_context.c
+++ b/src/mesa/drivers/dri/i915/i915_context.c
@@ -138,9 +138,6 @@ i915CreateContext(const __GLcontextModes * mesaVis,
    _tnl_destroy_pipeline(ctx);
    _tnl_install_pipeline(ctx, intel_pipeline);
 
-   if (intel->no_rast)
-      FALLBACK(intel, INTEL_FALLBACK_USER, 1);
-
    ctx->Const.MaxTextureUnits = I915_TEX_UNITS;
    ctx->Const.MaxTextureImageUnits = I915_TEX_UNITS;
    ctx->Const.MaxTextureCoordUnits = I915_TEX_UNITS;
diff --git a/src/mesa/drivers/dri/i915/i915_reg.h b/src/mesa/drivers/dri/i915/i915_reg.h
index 8891e11c6fd..b5585e70e79 100644
--- a/src/mesa/drivers/dri/i915/i915_reg.h
+++ b/src/mesa/drivers/dri/i915/i915_reg.h
@@ -325,6 +325,118 @@
 #define SCISSOR_RECT_0_YMAX(x)		((x)<<16)
 #define SCISSOR_RECT_0_XMAX(x)		(x)
 
+/* p189 */
+#define _3DSTATE_LOAD_STATE_IMMEDIATE_1   ((0x3<<29)|(0x1d<<24)|(0x04<<16))
+#define I1_LOAD_S(n)                      (1<<(4+n))
+
+#define S0_VB_OFFSET_MASK              0xffffffc
+#define S0_AUTO_CACHE_INV_DISABLE      (1<<0)
+
+#define S1_VERTEX_WIDTH_SHIFT          24
+#define S1_VERTEX_WIDTH_MASK           (0x3f<<24)
+#define S1_VERTEX_PITCH_SHIFT          16
+#define S1_VERTEX_PITCH_MASK           (0x3f<<16)
+
+#define TEXCOORDFMT_2D                 0x0
+#define TEXCOORDFMT_3D                 0x1
+#define TEXCOORDFMT_4D                 0x2
+#define TEXCOORDFMT_1D                 0x3
+#define TEXCOORDFMT_2D_16              0x4
+#define TEXCOORDFMT_4D_16              0x5
+#define TEXCOORDFMT_NOT_PRESENT        0xf
+#define S2_TEXCOORD_FMT0_MASK            0xf
+#define S2_TEXCOORD_FMT1_SHIFT           4
+#define S2_TEXCOORD_FMT(unit, type)    ((type)<<(unit*4))
+#define S2_TEXCOORD_NONE               (~0)
+
+/* S3 not interesting */
+
+#define S4_POINT_WIDTH_SHIFT           23
+#define S4_POINT_WIDTH_MASK            (0x1ff<<23)
+#define S4_LINE_WIDTH_SHIFT            19
+#define S4_LINE_WIDTH_ONE              (0x2<<19)
+#define S4_LINE_WIDTH_MASK             (0xf<<19)
+#define S4_FLATSHADE_ALPHA             (1<<18)
+#define S4_FLATSHADE_FOG               (1<<17)
+#define S4_FLATSHADE_SPECULAR          (1<<16)
+#define S4_FLATSHADE_COLOR             (1<<15)
+#define S4_CULLMODE_BOTH	       (0<<13)
+#define S4_CULLMODE_NONE	       (1<<13)
+#define S4_CULLMODE_CW		       (2<<13)
+#define S4_CULLMODE_CCW		       (3<<13)
+#define S4_CULLMODE_MASK	       (3<<13)
+#define S4_VFMT_POINT_WIDTH            (1<<12)
+#define S4_VFMT_SPEC_FOG               (1<<11)
+#define S4_VFMT_COLOR                  (1<<10)
+#define S4_VFMT_DEPTH_OFFSET           (1<<9)
+#define S4_VFMT_XYZ     	       (1<<6)
+#define S4_VFMT_XYZW     	       (2<<6)
+#define S4_VFMT_XY     		       (3<<6)
+#define S4_VFMT_XYW     	       (4<<6)
+#define S4_VFMT_XYZW_MASK              (7<<6)
+#define S4_FORCE_DEFAULT_DIFFUSE       (1<<5)
+#define S4_FORCE_DEFAULT_SPECULAR      (1<<4)
+#define S4_LOCAL_DEPTH_OFFSET_ENABLE   (1<<3)
+#define S4_VFMT_FOG_PARAM              (1<<2)
+#define S4_SPRITE_POINT_ENABLE         (1<<1)
+#define S4_LINE_ANTIALIAS_ENABLE       (1<<0)
+
+#define S4_VFMT_MASK (S4_VFMT_POINT_WIDTH   | 	\
+		      S4_VFMT_SPEC_FOG      |	\
+		      S4_VFMT_COLOR         |	\
+		      S4_VFMT_DEPTH_OFFSET  |	\
+		      S4_VFMT_XYZW_MASK     |	\
+		      S4_VFMT_FOG_PARAM)
+
+
+#define S5_WRITEDISABLE_ALPHA          (1<<31)
+#define S5_WRITEDISABLE_RED            (1<<30)
+#define S5_WRITEDISABLE_GREEN          (1<<29)
+#define S5_WRITEDISABLE_BLUE           (1<<28)
+#define S5_WRITEDISABLE_MASK           (0xf<<28)
+#define S5_FORCE_DEFAULT_POINT_SIZE    (1<<27)
+#define S5_LAST_PIXEL_ENABLE           (1<<26)
+#define S5_GLOBAL_DEPTH_OFFSET_ENABLE  (1<<25)
+#define S5_FOG_ENABLE                  (1<<24)
+#define S5_STENCIL_REF_SHIFT           16
+#define S5_STENCIL_REF_MASK            (0xff<<16)
+#define S5_STENCIL_TEST_FUNC_SHIFT     13
+#define S5_STENCIL_TEST_FUNC_MASK      (0x7<<13)
+#define S5_STENCIL_FAIL_SHIFT          10
+#define S5_STENCIL_FAIL_MASK           (0x7<<10)
+#define S5_STENCIL_PASS_Z_FAIL_SHIFT   7
+#define S5_STENCIL_PASS_Z_FAIL_MASK    (0x7<<7)
+#define S5_STENCIL_PASS_Z_PASS_SHIFT   4
+#define S5_STENCIL_PASS_Z_PASS_MASK    (0x7<<4)
+#define S5_STENCIL_WRITE_ENABLE        (1<<3)
+#define S5_STENCIL_TEST_ENABLE         (1<<2)
+#define S5_COLOR_DITHER_ENABLE         (1<<1)
+#define S5_LOGICOP_ENABLE              (1<<0)
+
+
+#define S6_ALPHA_TEST_ENABLE           (1<<31)
+#define S6_ALPHA_TEST_FUNC_SHIFT       28
+#define S6_ALPHA_TEST_FUNC_MASK        (0x7<<28)
+#define S6_ALPHA_REF_SHIFT             20
+#define S6_ALPHA_REF_MASK              (0xff<<20)
+#define S6_DEPTH_TEST_ENABLE           (1<<19)
+#define S6_DEPTH_TEST_FUNC_SHIFT       16
+#define S6_DEPTH_TEST_FUNC_MASK        (0x7<<16)
+#define S6_CBUF_BLEND_ENABLE           (1<<15)
+#define S6_CBUF_BLEND_FUNC_SHIFT       12
+#define S6_CBUF_BLEND_FUNC_MASK        (0x7<<12)
+#define S6_CBUF_SRC_BLEND_FACT_SHIFT   8
+#define S6_CBUF_SRC_BLEND_FACT_MASK    (0xf<<8)
+#define S6_CBUF_DST_BLEND_FACT_SHIFT   4
+#define S6_CBUF_DST_BLEND_FACT_MASK    (0xf<<4)
+#define S6_DEPTH_WRITE_ENABLE          (1<<3)
+#define S6_COLOR_WRITE_ENABLE          (1<<2)
+#define S6_TRISTRIP_PV_SHIFT           0
+#define S6_TRISTRIP_PV_MASK            (0x3<<0)
+
+#define S7_DEPTH_OFFSET_CONST_MASK     ~0
+
+
 /* Helper macros for blend factors
  */
 #define DST_BLND_FACT(f) ((f)<<S6_CBUF_DST_BLEND_FACT_SHIFT)
@@ -743,4 +855,10 @@
 #define _3DSTATE_DEFAULT_DIFFUSE    ((0x3<<29)|(0x1d<<24)|(0x99<<16))
 #define _3DSTATE_DEFAULT_SPECULAR   ((0x3<<29)|(0x1d<<24)|(0x9a<<16))
 
+
+#define MI_FLUSH                   ((0<<29)|(4<<23))
+#define FLUSH_MAP_CACHE            (1<<0)
+#define INHIBIT_FLUSH_RENDER_CACHE (1<<2)
+
+
 #endif
diff --git a/src/mesa/drivers/dri/i915/i915_vtbl.c b/src/mesa/drivers/dri/i915/i915_vtbl.c
index 19f2206285d..135bfaa265d 100644
--- a/src/mesa/drivers/dri/i915/i915_vtbl.c
+++ b/src/mesa/drivers/dri/i915/i915_vtbl.c
@@ -39,7 +39,6 @@
 #include "intel_batchbuffer.h"
 #include "intel_tex.h"
 #include "intel_regions.h"
-#include "intel_tris.h"
 
 #include "i915_reg.h"
 #include "i915_context.h"
@@ -297,9 +296,9 @@ i915_emit_state(struct intel_context *intel)
 {
    struct i915_context *i915 = i915_context(&intel->ctx);
    struct i915_hw_state *state = i915->current;
-   int i, count, aper_count;
+   int i;
+   int ret, count;
    GLuint dirty;
-   dri_bo *aper_array[3 + I915_TEX_UNITS];
    GET_CURRENT_CONTEXT(ctx);
    BATCH_LOCALS;
 
@@ -314,32 +313,28 @@ i915_emit_state(struct intel_context *intel)
     * Set the space as LOOP_CLIPRECTS now, since that's what our primitives
     * will be emitted under.
     */
-   intel_batchbuffer_require_space(intel->batch,
-				   get_state_size(state) + INTEL_PRIM_EMIT_SIZE,
+   intel_batchbuffer_require_space(intel->batch, get_state_size(state) + 8,
 				   LOOP_CLIPRECTS);
    count = 0;
  again:
-   aper_count = 0;
    dirty = get_dirty(state);
 
-   aper_array[aper_count++] = intel->batch->buf;
+   ret = 0;
    if (dirty & I915_UPLOAD_BUFFERS) {
-      aper_array[aper_count++] = state->draw_region->buffer;
-      if (state->depth_region)
-	 aper_array[aper_count++] = state->depth_region->buffer;
+     ret |= dri_bufmgr_check_aperture_space(state->draw_region->buffer);
+     if (state->depth_region)
+        ret |= dri_bufmgr_check_aperture_space(state->depth_region->buffer);
    }
 
    if (dirty & I915_UPLOAD_TEX_ALL) {
-      for (i = 0; i < I915_TEX_UNITS; i++) {
-	 if (dirty & I915_UPLOAD_TEX(i)) {
-	    if (state->tex_buffer[i]) {
-	       aper_array[aper_count++] = state->tex_buffer[i];
-	    }
-	 }
-      }
+     for (i = 0; i < I915_TEX_UNITS; i++)
+       if (dirty & I915_UPLOAD_TEX(i)) {
+	   if (state->tex_buffer[i]) {
+	       ret |= dri_bufmgr_check_aperture_space(state->tex_buffer[i]);
+	   }
+       }
    }
-
-   if (dri_bufmgr_check_aperture_space(aper_array, aper_count)) {
+   if (ret) {
        if (count == 0) {
 	   count++;
 	   intel_batchbuffer_flush(intel->batch);
@@ -382,14 +377,14 @@ i915_emit_state(struct intel_context *intel)
       OUT_BATCH(state->Buffer[I915_DESTREG_CBUFADDR0]);
       OUT_BATCH(state->Buffer[I915_DESTREG_CBUFADDR1]);
       OUT_RELOC(state->draw_region->buffer,
-		I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
+                DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_WRITE,
                 state->draw_region->draw_offset);
 
       if (state->depth_region) {
          OUT_BATCH(state->Buffer[I915_DESTREG_DBUFADDR0]);
          OUT_BATCH(state->Buffer[I915_DESTREG_DBUFADDR1]);
          OUT_RELOC(state->depth_region->buffer,
-		   I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
+                   DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_WRITE,
                    state->depth_region->draw_offset);
       }
 
@@ -432,7 +427,7 @@ i915_emit_state(struct intel_context *intel)
 
             if (state->tex_buffer[i]) {
                OUT_RELOC(state->tex_buffer[i],
-			 I915_GEM_DOMAIN_SAMPLER, 0,
+                         DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_READ,
                          state->tex_offset[i]);
             }
             else if (state == &i915->meta) {
@@ -634,5 +629,4 @@ i915InitVtbl(struct i915_context *i915)
    i915->intel.vtbl.flush_cmd = i915_flush_cmd;
    i915->intel.vtbl.assert_not_dirty = i915_assert_not_dirty;
    i915->intel.vtbl.note_unlock = i915_note_unlock; 
-   i915->intel.vtbl.finish_batch = intel_finish_vb;
 }
diff --git a/src/mesa/drivers/dri/i915/intel_bufmgr_ttm.c b/src/mesa/drivers/dri/i915/intel_bufmgr_ttm.c
new file mode 120000
index 00000000000..e9df5c62794
--- /dev/null
+++ b/src/mesa/drivers/dri/i915/intel_bufmgr_ttm.c
@@ -0,0 +1 @@
+../intel/intel_bufmgr_ttm.c
\ No newline at end of file
diff --git a/src/mesa/drivers/dri/i915/intel_pixel_read.c b/src/mesa/drivers/dri/i915/intel_pixel_read.c
index d009590a4bc..2e31656e984 100644
--- a/src/mesa/drivers/dri/i915/intel_pixel_read.c
+++ b/src/mesa/drivers/dri/i915/intel_pixel_read.c
@@ -173,6 +173,7 @@ do_blit_readpixels(GLcontext * ctx,
    struct intel_buffer_object *dst = intel_buffer_object(pack->BufferObj);
    GLuint dst_offset;
    GLuint rowLength;
+   dri_fence *fence = NULL;
 
    if (INTEL_DEBUG & DEBUG_PIXEL)
       _mesa_printf("%s\n", __FUNCTION__);
@@ -263,7 +264,7 @@ do_blit_readpixels(GLcontext * ctx,
 
          intelEmitCopyBlit(intel,
                            src->cpp,
-                           src->pitch, src->buffer, 0, src->tiling,
+                           src->pitch, src->buffer, 0, src->tiled,
                            rowLength, dst_buffer, dst_offset, GL_FALSE,
                            rect.x1,
                            rect.y1,
@@ -272,9 +273,19 @@ do_blit_readpixels(GLcontext * ctx,
                            rect.x2 - rect.x1, rect.y2 - rect.y1,
 			   GL_COPY);
       }
+
+      intel_batchbuffer_flush(intel->batch);
+      fence = intel->batch->last_fence;
+      dri_fence_reference(fence);
+
    }
    UNLOCK_HARDWARE(intel);
 
+   if (fence) {
+      dri_fence_wait(fence);
+      dri_fence_unreference(fence);
+   }
+
    if (INTEL_DEBUG & DEBUG_PIXEL)
       _mesa_printf("%s - DONE\n", __FUNCTION__);
 
diff --git a/src/mesa/drivers/dri/i915/intel_render.c b/src/mesa/drivers/dri/i915/intel_render.c
index 838d450378c..5e6500cfa1b 100644
--- a/src/mesa/drivers/dri/i915/intel_render.c
+++ b/src/mesa/drivers/dri/i915/intel_render.c
@@ -67,7 +67,7 @@
 
 #define HAVE_ELTS        0
 
-static uint32_t hw_prim[GL_POLYGON + 1] = {
+static GLuint hw_prim[GL_POLYGON + 1] = {
    0,
    PRIM3D_LINELIST,
    PRIM3D_LINESTRIP,
@@ -114,7 +114,7 @@ intelDmaPrimitive(struct intel_context *intel, GLenum prim)
       fprintf(stderr, "%s %s\n", __FUNCTION__, _mesa_lookup_enum_by_nr(prim));
    INTEL_FIREVERTICES(intel);
    intel->vtbl.reduced_primitive_state(intel, reduced_prim[prim]);
-   intel_set_prim(intel, hw_prim[prim]);
+   intelStartInlinePrimitive(intel, hw_prim[prim], LOOP_CLIPRECTS);
 }
 
 
@@ -126,11 +126,12 @@ do {						\
 
 #define FLUSH() INTEL_FIREVERTICES(intel)
 
-#define GET_SUBSEQUENT_VB_MAX_VERTS() (INTEL_VB_SIZE / (intel->vertex_size * 4))
-#define GET_CURRENT_VB_MAX_VERTS() \
-   ((INTEL_VB_SIZE - intel->prim.current_offset) / (intel->vertex_size * 4))
+#define GET_SUBSEQUENT_VB_MAX_VERTS() \
+  ((intel->batch->size - 1500) / (intel->vertex_size*4))
+#define GET_CURRENT_VB_MAX_VERTS() GET_SUBSEQUENT_VB_MAX_VERTS()
 
-#define ALLOC_VERTS(nr) intel_get_prim_space(intel, nr)
+#define ALLOC_VERTS( nr ) \
+   intelExtendInlinePrimitive( intel, (nr) * intel->vertex_size )
 
 #define EMIT_VERTS( ctx, j, nr, buf ) \
   _tnl_emit_vertices_to_buffer(ctx, j, (j)+(nr), buf )
diff --git a/src/mesa/drivers/dri/i915/intel_tris.c b/src/mesa/drivers/dri/i915/intel_tris.c
index 5f4b852212a..bbb4e0f3cda 100644
--- a/src/mesa/drivers/dri/i915/intel_tris.c
+++ b/src/mesa/drivers/dri/i915/intel_tris.c
@@ -25,12 +25,6 @@
  * 
  **************************************************************************/
 
-/** @file intel_tris.c
- *
- * This file contains functions for managing the vertex buffer and emitting
- * primitives into it.
- */
-
 #include "glheader.h"
 #include "context.h"
 #include "macros.h"
@@ -53,185 +47,111 @@
 #include "intel_reg.h"
 #include "intel_span.h"
 #include "intel_tex.h"
-#include "intel_chipset.h"
-#include "i830_context.h"
-#include "i830_reg.h"
 
 static void intelRenderPrimitive(GLcontext * ctx, GLenum prim);
 static void intelRasterPrimitive(GLcontext * ctx, GLenum rprim,
                                  GLuint hwprim);
 
-/** Sets the primitive type for a primitive sequence, flushing as needed. */
-void intel_set_prim(struct intel_context *intel, uint32_t prim)
+/*
+ */
+static void
+intel_flush_inline_primitive(struct intel_context *intel)
 {
-   if (prim != intel->prim.primitive) {
-      INTEL_FIREVERTICES(intel);
-      intel->prim.primitive = prim;
-   }
-}
+   GLuint used = intel->batch->ptr - intel->prim.start_ptr;
 
-/** Returns mapped VB space for the given number of vertices */
-uint32_t *intel_get_prim_space(struct intel_context *intel, unsigned int count)
-{
-   uint32_t *addr;
-
-   /* Check for space in the existing VB */
-   if (intel->prim.vb_bo == NULL ||
-       (intel->prim.current_offset +
-	count * intel->vertex_size * 4) > INTEL_VB_SIZE ||
-       (intel->prim.count + count) >= (1 << 16)) {
-      /* Flush existing prim if any */
-      INTEL_FIREVERTICES(intel);
+   assert(intel->prim.primitive != ~0);
 
-      intel_finish_vb(intel);
+/*    _mesa_printf("/\n"); */
 
-      /* Start a new VB */
-      if (intel->prim.vb == NULL)
-	 intel->prim.vb = malloc(INTEL_VB_SIZE);
-      intel->prim.vb_bo = dri_bo_alloc(intel->bufmgr, "vb",
-				       INTEL_VB_SIZE, 4);
-      intel->prim.start_offset = 0;
-      intel->prim.current_offset = 0;
-   }
+   if (used < 8)
+      goto do_discard;
+
+   *(int *) intel->prim.start_ptr = (_3DPRIMITIVE |
+                                     intel->prim.primitive | (used / 4 - 2));
 
-   intel->prim.flush = intel_flush_prim;
+   goto finished;
 
-   addr = (uint32_t *)(intel->prim.vb + intel->prim.current_offset);
-   intel->prim.current_offset += intel->vertex_size * 4 * count;
-   intel->prim.count += count;
+ do_discard:
+   intel->batch->ptr -= used;
 
-   return addr;
+ finished:
+   intel->prim.primitive = ~0;
+   intel->prim.start_ptr = 0;
+   intel->prim.flush = 0;
 }
 
-/** Dispatches the accumulated primitive to the batchbuffer. */
-void intel_flush_prim(struct intel_context *intel)
+
+/* Emit a primitive referencing vertices in a vertex buffer.
+ */
+void
+intelStartInlinePrimitive(struct intel_context *intel,
+                          GLuint prim, GLuint batch_flags)
 {
    BATCH_LOCALS;
-   dri_bo *aper_array[2];
-   dri_bo *vb_bo;
-
-   /* Must be called after an intel_start_prim. */
-   assert(intel->prim.primitive != ~0);
-
-   if (intel->prim.count == 0)
-      return;
-
-   /* Keep a reference on the BO as it may get finished as we start the
-    * batch emit.
-    */
-   vb_bo = intel->prim.vb_bo;
-   dri_bo_reference(vb_bo);
 
    intel_wait_flips(intel);
 
    intel->vtbl.emit_state(intel);
 
-   aper_array[0] = intel->batch->buf;
-   aper_array[1] = vb_bo;
-   if (dri_bufmgr_check_aperture_space(aper_array, 2)) {
-      intel_batchbuffer_flush(intel->batch);
-      intel->vtbl.emit_state(intel);
-   }
-
-   /* Ensure that we don't start a new batch for the following emit, which
-    * depends on the state just emitted. emit_state should be making sure we
-    * have the space for this.
-    */
    intel->no_batch_wrap = GL_TRUE;
 
-   /* Check that we actually emitted the state into this batch, using the
-    * UPLOAD_CTX bit as the signal.
+/*    _mesa_printf("%s *", __progname); */
+
+   /* Emit a slot which will be filled with the inline primitive
+    * command later.
     */
+   BEGIN_BATCH(2, batch_flags);
+   OUT_BATCH(0);
+
    assert((intel->batch->dirty_state & (1<<1)) == 0);
 
-#if 0
-   printf("emitting %d..%d=%d vertices size %d\n", intel->prim.start_offset,
-	  intel->prim.current_offset, intel->prim.count,
-	  intel->vertex_size * 4);
-#endif
+   intel->prim.start_ptr = intel->batch->ptr;
+   intel->prim.primitive = prim;
+   intel->prim.flush = intel_flush_inline_primitive;
 
-   if (IS_9XX(intel->intelScreen->deviceID)) {
-      BEGIN_BATCH(5, LOOP_CLIPRECTS);
-      OUT_BATCH(_3DSTATE_LOAD_STATE_IMMEDIATE_1 |
-		I1_LOAD_S(0) | I1_LOAD_S(1) | 1);
-      assert((intel->prim.start_offset & !S0_VB_OFFSET_MASK) == 0);
-      OUT_RELOC(vb_bo, I915_GEM_DOMAIN_VERTEX, 0,
-		intel->prim.start_offset);
-      OUT_BATCH((intel->vertex_size << S1_VERTEX_WIDTH_SHIFT) |
-		(intel->vertex_size << S1_VERTEX_PITCH_SHIFT));
-
-      OUT_BATCH(_3DPRIMITIVE |
-		PRIM_INDIRECT |
-		PRIM_INDIRECT_SEQUENTIAL |
-		intel->prim.primitive |
-		intel->prim.count);
-      OUT_BATCH(0); /* Beginning vertex index */
-      ADVANCE_BATCH();
-   } else {
-      struct i830_context *i830 = i830_context(&intel->ctx);
-
-      BEGIN_BATCH(5, LOOP_CLIPRECTS);
-      OUT_BATCH(_3DSTATE_LOAD_STATE_IMMEDIATE_1 |
-		I1_LOAD_S(0) | I1_LOAD_S(2) | 1);
-      /* S0 */
-      assert((intel->prim.start_offset & !S0_VB_OFFSET_MASK_830) == 0);
-      OUT_RELOC(vb_bo, I915_GEM_DOMAIN_VERTEX, 0,
-		intel->prim.start_offset |
-		(intel->vertex_size << S0_VB_PITCH_SHIFT_830) |
-		S0_VB_ENABLE_830);
-      /* S1
-       * This is somewhat unfortunate -- VB width is tied up with
-       * vertex format data that we've already uploaded through
-       * _3DSTATE_VFT[01]_CMD.  We may want to replace emits of VFT state with
-       * STATE_IMMEDIATE_1 like this to avoid duplication.
-       */
-      OUT_BATCH((i830->state.Ctx[I830_CTXREG_VF] & VFT0_TEX_COUNT_MASK) >>
-		VFT0_TEX_COUNT_SHIFT << S2_TEX_COUNT_SHIFT_830 |
-		(i830->state.Ctx[I830_CTXREG_VF2] << 16) |
-		intel->vertex_size << S2_VERTEX_0_WIDTH_SHIFT_830);
-
-      OUT_BATCH(_3DPRIMITIVE |
-		PRIM_INDIRECT |
-		PRIM_INDIRECT_SEQUENTIAL |
-		intel->prim.primitive |
-		intel->prim.count);
-      OUT_BATCH(0); /* Beginning vertex index */
-      ADVANCE_BATCH();
-   }
+   OUT_BATCH(0);
+   ADVANCE_BATCH();
 
    intel->no_batch_wrap = GL_FALSE;
 
-   intel->prim.flush = NULL;
-   intel->prim.start_offset = intel->prim.current_offset;
-   if (!IS_9XX(intel->intelScreen->deviceID))
-      intel->prim.start_offset = ALIGN(intel->prim.start_offset, 128);
-   intel->prim.count = 0;
+/*    _mesa_printf(">"); */
+}
+
+
+void
+intelWrapInlinePrimitive(struct intel_context *intel)
+{
+   GLuint prim = intel->prim.primitive;
+   enum cliprect_mode cliprect_mode = intel->batch->cliprect_mode;
 
-   dri_bo_unreference(vb_bo);
+   intel_flush_inline_primitive(intel);
+   intel_batchbuffer_flush(intel->batch);
+   intelStartInlinePrimitive(intel, prim, cliprect_mode);  /* ??? */
 }
 
-/**
- * Uploads the locally-accumulated VB into the buffer object.
- *
- * This avoids us thrashing the cachelines in and out as the buffer gets
- * filled, dispatched, then reused as the hardware completes rendering from it,
- * and also lets us clflush less if we dispatch with a partially-filled VB.
- *
- * This is called normally from get_space when we're finishing a BO, but also
- * at batch flush time so that we don't try accessing the contents of a
- * just-dispatched buffer.
- */
-void intel_finish_vb(struct intel_context *intel)
+GLuint *
+intelExtendInlinePrimitive(struct intel_context *intel, GLuint dwords)
 {
-   if (intel->prim.vb_bo == NULL)
-      return;
+   GLuint sz = dwords * sizeof(GLuint);
+   GLuint *ptr;
+
+   assert(intel->prim.flush == intel_flush_inline_primitive);
+
+   if (intel_batchbuffer_space(intel->batch) < sz)
+      intelWrapInlinePrimitive(intel);
+
+/*    _mesa_printf("."); */
+
+   intel->vtbl.assert_not_dirty(intel);
 
-   dri_bo_subdata(intel->prim.vb_bo, 0, intel->prim.start_offset,
-		  intel->prim.vb);
-   dri_bo_unreference(intel->prim.vb_bo);
-   intel->prim.vb_bo = NULL;
+   ptr = (GLuint *) intel->batch->ptr;
+   intel->batch->ptr += sz;
+
+   return ptr;
 }
 
+
+
 /***********************************************************************
  *                    Emit primitives as inline vertices               *
  ***********************************************************************/
@@ -262,7 +182,7 @@ intel_draw_quad(struct intel_context *intel,
                 intelVertexPtr v1, intelVertexPtr v2, intelVertexPtr v3)
 {
    GLuint vertsize = intel->vertex_size;
-   GLuint *vb = intel_get_prim_space(intel, 6);
+   GLuint *vb = intelExtendInlinePrimitive(intel, 6 * vertsize);
    int j;
 
    COPY_DWORDS(j, vb, vertsize, v0);
@@ -290,7 +210,7 @@ intel_draw_triangle(struct intel_context *intel,
                     intelVertexPtr v0, intelVertexPtr v1, intelVertexPtr v2)
 {
    GLuint vertsize = intel->vertex_size;
-   GLuint *vb = intel_get_prim_space(intel, 3);
+   GLuint *vb = intelExtendInlinePrimitive(intel, 3 * vertsize);
    int j;
 
    COPY_DWORDS(j, vb, vertsize, v0);
@@ -304,7 +224,7 @@ intel_draw_line(struct intel_context *intel,
                 intelVertexPtr v0, intelVertexPtr v1)
 {
    GLuint vertsize = intel->vertex_size;
-   GLuint *vb = intel_get_prim_space(intel, 2);
+   GLuint *vb = intelExtendInlinePrimitive(intel, 2 * vertsize);
    int j;
 
    COPY_DWORDS(j, vb, vertsize, v0);
@@ -316,7 +236,7 @@ static void
 intel_draw_point(struct intel_context *intel, intelVertexPtr v0)
 {
    GLuint vertsize = intel->vertex_size;
-   GLuint *vb = intel_get_prim_space(intel, 1);
+   GLuint *vb = intelExtendInlinePrimitive(intel, vertsize);
    int j;
 
    /* Adjust for sub pixel position -- still required for conform. */
@@ -825,7 +745,7 @@ intelFastRenderClippedPoly(GLcontext * ctx, const GLuint * elts, GLuint n)
 {
    struct intel_context *intel = intel_context(ctx);
    const GLuint vertsize = intel->vertex_size;
-   GLuint *vb = intel_get_prim_space(intel, (n - 2) * 3);
+   GLuint *vb = intelExtendInlinePrimitive(intel, (n - 2) * 3 * vertsize);
    GLubyte *vertptr = (GLubyte *) intel->verts;
    const GLuint *start = (const GLuint *) V(elts[0]);
    int i, j;
@@ -1030,7 +950,7 @@ intelRasterPrimitive(GLcontext * ctx, GLenum rprim, GLuint hwprim)
    if (hwprim != intel->prim.primitive) {
       INTEL_FIREVERTICES(intel);
 
-      intel_set_prim(intel, hwprim);
+      intelStartInlinePrimitive(intel, hwprim, LOOP_CLIPRECTS);
    }
 }
 
@@ -1163,18 +1083,15 @@ intel_meta_draw_poly(struct intel_context *intel,
    union fi *vb;
    GLint i;
    GLboolean was_locked = intel->locked;
-   unsigned int saved_vertex_size = intel->vertex_size;
 
    if (!was_locked)
        LOCK_HARDWARE(intel);
 
-   intel->vertex_size = 6;
-
    /* All 3d primitives should be emitted with LOOP_CLIPRECTS,
     * otherwise the drawing origin (DR4) might not be set correctly.
     */
-   intel_set_prim(intel, PRIM3D_TRIFAN);
-   vb = (union fi *) intel_get_prim_space(intel, n);
+   intelStartInlinePrimitive(intel, PRIM3D_TRIFAN, LOOP_CLIPRECTS);
+   vb = (union fi *) intelExtendInlinePrimitive(intel, n * 6);
 
    for (i = 0; i < n; i++) {
       vb[0].f = xy[i][0];
@@ -1188,8 +1105,6 @@ intel_meta_draw_poly(struct intel_context *intel,
 
    INTEL_FIREVERTICES(intel);
 
-   intel->vertex_size = saved_vertex_size;
-
    if (!was_locked)
        UNLOCK_HARDWARE(intel);
 }
diff --git a/src/mesa/drivers/dri/i915/intel_tris.h b/src/mesa/drivers/dri/i915/intel_tris.h
index 0e08986221f..021e5c64500 100644
--- a/src/mesa/drivers/dri/i915/intel_tris.h
+++ b/src/mesa/drivers/dri/i915/intel_tris.h
@@ -30,9 +30,7 @@
 
 #include "mtypes.h"
 
-#define INTEL_VB_SIZE		(32 * 1024)
-/** 3 dwords of state_immediate and 2 of 3dprim, in intel_flush_prim */
-#define INTEL_PRIM_EMIT_SIZE	(5 * 4)
+
 
 #define _INTEL_NEW_RENDERSTATE (_DD_NEW_LINE_STIPPLE |		\
 			       _DD_NEW_TRI_UNFILLED |		\
@@ -46,9 +44,11 @@ extern void intelInitTriFuncs(GLcontext * ctx);
 
 extern void intelChooseRenderState(GLcontext * ctx);
 
-void intel_set_prim(struct intel_context *intel, uint32_t prim);
-GLuint *intel_get_prim_space(struct intel_context *intel, unsigned int count);
-void intel_flush_prim(struct intel_context *intel);
-void intel_finish_vb(struct intel_context *intel);
+extern void intelStartInlinePrimitive(struct intel_context *intel,
+                                      GLuint prim, GLuint flags);
+extern void intelWrapInlinePrimitive(struct intel_context *intel);
+
+GLuint *intelExtendInlinePrimitive(struct intel_context *intel,
+                                   GLuint dwords);
 
 #endif