diff options
| author | Chad Versace <[email protected]> | 2016-01-05 14:28:28 -0800 |
|---|---|---|
| committer | Chad Versace <[email protected]> | 2016-01-06 09:38:57 -0800 |
| commit | eea2d4d05987b4f8ad90a1588267f9495f1e9e99 (patch) | |
| tree | 67ff7687b7cbda1a6c7c9644320a8a5c316f2c2d /src/isl | |
| parent | 39d043f94a6c09d57d7dfcb15d2e5d913c85d611 (diff) | |
isl: Don't align phys_slice0_sa.width twice
It's already aligned to the format's block width. Don't align it again
in isl_calc_row_pitch().
Diffstat (limited to 'src/isl')
| -rw-r--r-- | src/isl/isl.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/isl/isl.c b/src/isl/isl.c index 4a1c9f4a94a..72fc4b8d9e1 100644 --- a/src/isl/isl.c +++ b/src/isl/isl.c @@ -821,8 +821,8 @@ isl_calc_row_pitch(const struct isl_device *dev, * texels, and must be converted to bytes based on the surface format * being used to determine whether additional pages need to be defined. */ - row_pitch = MAX(row_pitch, - fmtl->bs * isl_align_div_npot(phys_slice0_sa->w, fmtl->bw)); + assert(phys_slice0_sa->w % fmtl->bw == 0); + row_pitch = MAX(row_pitch, fmtl->bs * phys_slice0_sa->w); switch (tile_info->tiling) { case ISL_TILING_LINEAR: |