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authorJason Ekstrand <[email protected]>2020-03-25 14:35:53 -0500
committerMarge Bot <[email protected]>2020-04-28 22:45:39 +0000
commit20e72e435c9650bca5da6b0c05a0fcec1fcd517a (patch)
treeb2fa4ee0e4a1f4bedfbac681c60e5692a2346594 /src/intel
parent814dc6693593c51d7d89da54ab6191dbf862397e (diff)
intel: Move swizzle_color_value from blorp to ISL
Reviewed-by: Rafael Antognolli <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4393>
Diffstat (limited to 'src/intel')
-rw-r--r--src/intel/blorp/blorp.h3
-rw-r--r--src/intel/blorp/blorp_clear.c29
-rw-r--r--src/intel/isl/isl.c23
-rw-r--r--src/intel/isl/isl.h4
4 files changed, 31 insertions, 28 deletions
diff --git a/src/intel/blorp/blorp.h b/src/intel/blorp/blorp.h
index dd31ef2e2dc..b88178266c3 100644
--- a/src/intel/blorp/blorp.h
+++ b/src/intel/blorp/blorp.h
@@ -161,9 +161,6 @@ blorp_buffer_copy(struct blorp_batch *batch,
struct blorp_address dst,
uint64_t size);
-union isl_color_value
-swizzle_color_value(union isl_color_value src, struct isl_swizzle swizzle);
-
void
blorp_fast_clear(struct blorp_batch *batch,
const struct blorp_surf *surf,
diff --git a/src/intel/blorp/blorp_clear.c b/src/intel/blorp/blorp_clear.c
index 3daeb004850..e79f602261e 100644
--- a/src/intel/blorp/blorp_clear.c
+++ b/src/intel/blorp/blorp_clear.c
@@ -364,33 +364,12 @@ blorp_fast_clear(struct blorp_batch *batch,
/* If a swizzle was provided, we need to swizzle the clear color so that
* the hardware color format conversion will work properly.
*/
- params.dst.clear_color = swizzle_color_value(params.dst.clear_color,
- swizzle);
+ params.dst.clear_color =
+ isl_color_value_swizzle_inv(params.dst.clear_color, swizzle);
batch->blorp->exec(batch, &params);
}
-union isl_color_value
-swizzle_color_value(union isl_color_value src, struct isl_swizzle swizzle)
-{
- union isl_color_value dst = { .u32 = { 0, } };
-
- /* We assign colors in ABGR order so that the first one will be taken in
- * RGBA precedence order. According to the PRM docs for shader channel
- * select, this matches Haswell hardware behavior.
- */
- if ((unsigned)(swizzle.a - ISL_CHANNEL_SELECT_RED) < 4)
- dst.u32[swizzle.a - ISL_CHANNEL_SELECT_RED] = src.u32[3];
- if ((unsigned)(swizzle.b - ISL_CHANNEL_SELECT_RED) < 4)
- dst.u32[swizzle.b - ISL_CHANNEL_SELECT_RED] = src.u32[2];
- if ((unsigned)(swizzle.g - ISL_CHANNEL_SELECT_RED) < 4)
- dst.u32[swizzle.g - ISL_CHANNEL_SELECT_RED] = src.u32[1];
- if ((unsigned)(swizzle.r - ISL_CHANNEL_SELECT_RED) < 4)
- dst.u32[swizzle.r - ISL_CHANNEL_SELECT_RED] = src.u32[0];
-
- return dst;
-}
-
void
blorp_clear(struct blorp_batch *batch,
const struct blorp_surf *surf,
@@ -408,7 +387,7 @@ blorp_clear(struct blorp_batch *batch,
* also ensures that they work on pre-Haswell hardware which can't swizlle
* at all.
*/
- clear_color = swizzle_color_value(clear_color, swizzle);
+ clear_color = isl_color_value_swizzle_inv(clear_color, swizzle);
swizzle = ISL_SWIZZLE_IDENTITY;
bool clear_rgb_as_red = false;
@@ -423,7 +402,7 @@ blorp_clear(struct blorp_batch *batch,
* around it by swapping the colors around and using B4G4R4A4 instead.
*/
const struct isl_swizzle ARGB = ISL_SWIZZLE(ALPHA, RED, GREEN, BLUE);
- clear_color = swizzle_color_value(clear_color, ARGB);
+ clear_color = isl_color_value_swizzle_inv(clear_color, ARGB);
format = ISL_FORMAT_B4G4R4A4_UNORM;
} else if (isl_format_get_layout(format)->bpb % 3 == 0) {
clear_rgb_as_red = true;
diff --git a/src/intel/isl/isl.c b/src/intel/isl/isl.c
index 9aa377b7e4b..f7689d5b867 100644
--- a/src/intel/isl/isl.c
+++ b/src/intel/isl/isl.c
@@ -2896,6 +2896,29 @@ isl_swizzle_invert(struct isl_swizzle swizzle)
return (struct isl_swizzle) { chans[0], chans[1], chans[2], chans[3] };
}
+/** Applies an inverse swizzle to a color value */
+union isl_color_value
+isl_color_value_swizzle_inv(union isl_color_value src,
+ struct isl_swizzle swizzle)
+{
+ union isl_color_value dst = { .u32 = { 0, } };
+
+ /* We assign colors in ABGR order so that the first one will be taken in
+ * RGBA precedence order. According to the PRM docs for shader channel
+ * select, this matches Haswell hardware behavior.
+ */
+ if ((unsigned)(swizzle.a - ISL_CHANNEL_SELECT_RED) < 4)
+ dst.u32[swizzle.a - ISL_CHANNEL_SELECT_RED] = src.u32[3];
+ if ((unsigned)(swizzle.b - ISL_CHANNEL_SELECT_RED) < 4)
+ dst.u32[swizzle.b - ISL_CHANNEL_SELECT_RED] = src.u32[2];
+ if ((unsigned)(swizzle.g - ISL_CHANNEL_SELECT_RED) < 4)
+ dst.u32[swizzle.g - ISL_CHANNEL_SELECT_RED] = src.u32[1];
+ if ((unsigned)(swizzle.r - ISL_CHANNEL_SELECT_RED) < 4)
+ dst.u32[swizzle.r - ISL_CHANNEL_SELECT_RED] = src.u32[0];
+
+ return dst;
+}
+
uint8_t
isl_format_get_aux_map_encoding(enum isl_format format)
{
diff --git a/src/intel/isl/isl.h b/src/intel/isl/isl.h
index bfd20d058d9..80c801370d2 100644
--- a/src/intel/isl/isl.h
+++ b/src/intel/isl/isl.h
@@ -1683,6 +1683,10 @@ enum isl_format isl_format_rgb_to_rgba(enum isl_format rgb) ATTRIBUTE_CONST;
enum isl_format isl_format_rgb_to_rgbx(enum isl_format rgb) ATTRIBUTE_CONST;
enum isl_format isl_format_rgbx_to_rgba(enum isl_format rgb) ATTRIBUTE_CONST;
+union isl_color_value
+isl_color_value_swizzle_inv(union isl_color_value src,
+ struct isl_swizzle swizzle);
+
void isl_color_value_pack(const union isl_color_value *value,
enum isl_format format,
uint32_t *data_out);