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authorJason Ekstrand <[email protected]>2016-06-02 18:32:11 -0700
committerJason Ekstrand <[email protected]>2016-07-15 15:53:48 -0700
commitf8984b918a1db8869bae6a3ffa8883365342f98e (patch)
tree05fc0314b4d2d45eb73ab66e4871baa8f8c0995e /src/intel
parent815847e2b3db405f7f5a97459e6ed2f2b3b4d09e (diff)
isl: Add support for filling out surface states all the way back to gen4
Signed-off-by: Jason Ekstrand <[email protected]> Reviewed-by: Chad Versace <[email protected]>
Diffstat (limited to 'src/intel')
-rw-r--r--src/intel/isl/Android.mk60
-rw-r--r--src/intel/isl/Makefile.am12
-rw-r--r--src/intel/isl/Makefile.sources13
-rw-r--r--src/intel/isl/isl.c22
-rw-r--r--src/intel/isl/isl_priv.h24
-rw-r--r--src/intel/isl/isl_surface_state.c56
6 files changed, 182 insertions, 5 deletions
diff --git a/src/intel/isl/Android.mk b/src/intel/isl/Android.mk
index c828c5cd6bf..e2771ad320f 100644
--- a/src/intel/isl/Android.mk
+++ b/src/intel/isl/Android.mk
@@ -30,6 +30,63 @@ LIBISL_GENX_COMMON_INCLUDES := \
$(MESA_TOP)/src/mesa/drivers/dri/i965
# ---------------------------------------
+# Build libisl_gen4
+# ---------------------------------------
+
+include $(CLEAR_VARS)
+
+LOCAL_MODULE := libmesa_isl_gen4
+
+LOCAL_SRC_FILES := $(ISL_GEN4_FILES)
+
+LOCAL_CFLAGS := -DGEN_VERSIONx10=40
+
+LOCAL_C_INCLUDES := $(LIBISL_GENX_COMMON_INCLUDES)
+
+LOCAL_WHOLE_STATIC_LIBRARIES := libmesa_genxml
+
+include $(MESA_COMMON_MK)
+include $(BUILD_STATIC_LIBRARY)
+
+# ---------------------------------------
+# Build libisl_gen5
+# ---------------------------------------
+
+include $(CLEAR_VARS)
+
+LOCAL_MODULE := libmesa_isl_gen5
+
+LOCAL_SRC_FILES := $(ISL_GEN5_FILES)
+
+LOCAL_CFLAGS := -DGEN_VERSIONx10=50
+
+LOCAL_C_INCLUDES := $(LIBISL_GENX_COMMON_INCLUDES)
+
+LOCAL_WHOLE_STATIC_LIBRARIES := libmesa_genxml
+
+include $(MESA_COMMON_MK)
+include $(BUILD_STATIC_LIBRARY)
+
+# ---------------------------------------
+# Build libisl_gen6
+# ---------------------------------------
+
+include $(CLEAR_VARS)
+
+LOCAL_MODULE := libmesa_isl_gen6
+
+LOCAL_SRC_FILES := $(ISL_GEN6_FILES)
+
+LOCAL_CFLAGS := -DGEN_VERSIONx10=60
+
+LOCAL_C_INCLUDES := $(LIBISL_GENX_COMMON_INCLUDES)
+
+LOCAL_WHOLE_STATIC_LIBRARIES := libmesa_genxml
+
+include $(MESA_COMMON_MK)
+include $(BUILD_STATIC_LIBRARY)
+
+# ---------------------------------------
# Build libisl_gen7
# ---------------------------------------
@@ -125,6 +182,9 @@ LOCAL_C_INCLUDES := \
LOCAL_EXPORT_C_INCLUDE_DIRS := $(MESA_TOP)/src/intel
LOCAL_WHOLE_STATIC_LIBRARIES := \
+ libmesa_isl_gen4 \
+ libmesa_isl_gen5 \
+ libmesa_isl_gen6 \
libmesa_isl_gen7 \
libmesa_isl_gen75 \
libmesa_isl_gen8 \
diff --git a/src/intel/isl/Makefile.am b/src/intel/isl/Makefile.am
index 1fd668371d7..7c22324d56c 100644
--- a/src/intel/isl/Makefile.am
+++ b/src/intel/isl/Makefile.am
@@ -22,6 +22,9 @@
include Makefile.sources
ISL_GEN_LIBS = \
+ libisl-gen4.la \
+ libisl-gen5.la \
+ libisl-gen6.la \
libisl-gen7.la \
libisl-gen75.la \
libisl-gen8.la \
@@ -52,6 +55,15 @@ libisl_la_LIBADD = $(ISL_GEN_LIBS)
libisl_la_SOURCES = $(ISL_FILES) $(ISL_GENERATED_FILES)
+libisl_gen4_la_SOURCES = $(ISL_GEN4_FILES)
+libisl_gen4_la_CFLAGS = $(libisl_la_CFLAGS) -DGEN_VERSIONx10=40
+
+libisl_gen5_la_SOURCES = $(ISL_GEN5_FILES)
+libisl_gen5_la_CFLAGS = $(libisl_la_CFLAGS) -DGEN_VERSIONx10=50
+
+libisl_gen6_la_SOURCES = $(ISL_GEN6_FILES)
+libisl_gen6_la_CFLAGS = $(libisl_la_CFLAGS) -DGEN_VERSIONx10=60
+
libisl_gen7_la_SOURCES = $(ISL_GEN7_FILES)
libisl_gen7_la_CFLAGS = $(libisl_la_CFLAGS) -DGEN_VERSIONx10=70
diff --git a/src/intel/isl/Makefile.sources b/src/intel/isl/Makefile.sources
index 89b1418ffc7..aa20ed4cb09 100644
--- a/src/intel/isl/Makefile.sources
+++ b/src/intel/isl/Makefile.sources
@@ -2,12 +2,21 @@ ISL_FILES = \
isl.c \
isl.h \
isl_format.c \
+ isl_priv.h \
+ isl_storage_image.c
+
+ISL_GEN4_FILES = \
isl_gen4.c \
isl_gen4.h \
+ isl_surface_state.c
+
+ISL_GEN5_FILES = \
+ isl_surface_state.c
+
+ISL_GEN6_FILES = \
isl_gen6.c \
isl_gen6.h \
- isl_priv.h \
- isl_storage_image.c
+ isl_surface_state.c
ISL_GEN7_FILES = \
isl_gen7.c \
diff --git a/src/intel/isl/isl.c b/src/intel/isl/isl.c
index 435cffd8a65..92658ec7af7 100644
--- a/src/intel/isl/isl.c
+++ b/src/intel/isl/isl.c
@@ -1276,6 +1276,20 @@ isl_surf_fill_state_s(const struct isl_device *dev, void *state,
}
switch (ISL_DEV_GEN(dev)) {
+ case 4:
+ if (ISL_DEV_IS_G4X(dev)) {
+ /* G45 surface state is the same as gen5 */
+ isl_gen5_surf_fill_state_s(dev, state, info);
+ } else {
+ isl_gen4_surf_fill_state_s(dev, state, info);
+ }
+ break;
+ case 5:
+ isl_gen5_surf_fill_state_s(dev, state, info);
+ break;
+ case 6:
+ isl_gen6_surf_fill_state_s(dev, state, info);
+ break;
case 7:
if (ISL_DEV_IS_HASWELL(dev)) {
isl_gen75_surf_fill_state_s(dev, state, info);
@@ -1299,6 +1313,14 @@ isl_buffer_fill_state_s(const struct isl_device *dev, void *state,
const struct isl_buffer_fill_state_info *restrict info)
{
switch (ISL_DEV_GEN(dev)) {
+ case 4:
+ case 5:
+ /* Gen 4-5 are all the same when it comes to buffer surfaces */
+ isl_gen5_buffer_fill_state_s(state, info);
+ break;
+ case 6:
+ isl_gen6_buffer_fill_state_s(state, info);
+ break;
case 7:
if (ISL_DEV_IS_HASWELL(dev)) {
isl_gen75_buffer_fill_state_s(state, info);
diff --git a/src/intel/isl/isl_priv.h b/src/intel/isl/isl_priv.h
index d98e7079541..3a7af1ae35f 100644
--- a/src/intel/isl/isl_priv.h
+++ b/src/intel/isl/isl_priv.h
@@ -136,6 +136,18 @@ isl_extent3d_el_to_sa(enum isl_format fmt, struct isl_extent3d extent_el)
}
void
+isl_gen4_surf_fill_state_s(const struct isl_device *dev, void *state,
+ const struct isl_surf_fill_state_info *restrict info);
+
+void
+isl_gen5_surf_fill_state_s(const struct isl_device *dev, void *state,
+ const struct isl_surf_fill_state_info *restrict info);
+
+void
+isl_gen6_surf_fill_state_s(const struct isl_device *dev, void *state,
+ const struct isl_surf_fill_state_info *restrict info);
+
+void
isl_gen7_surf_fill_state_s(const struct isl_device *dev, void *state,
const struct isl_surf_fill_state_info *restrict info);
@@ -150,6 +162,18 @@ isl_gen9_surf_fill_state_s(const struct isl_device *dev, void *state,
const struct isl_surf_fill_state_info *restrict info);
void
+isl_gen4_buffer_fill_state_s(void *state,
+ const struct isl_buffer_fill_state_info *restrict info);
+
+void
+isl_gen5_buffer_fill_state_s(void *state,
+ const struct isl_buffer_fill_state_info *restrict info);
+
+void
+isl_gen6_buffer_fill_state_s(void *state,
+ const struct isl_buffer_fill_state_info *restrict info);
+
+void
isl_gen7_buffer_fill_state_s(void *state,
const struct isl_buffer_fill_state_info *restrict info);
diff --git a/src/intel/isl/isl_surface_state.c b/src/intel/isl/isl_surface_state.c
index c8fe6700776..dcec800b640 100644
--- a/src/intel/isl/isl_surface_state.c
+++ b/src/intel/isl/isl_surface_state.c
@@ -78,11 +78,13 @@ static const uint8_t isl_to_gen_tiling[] = {
};
#endif
+#if GEN_GEN >= 7
static const uint32_t isl_to_gen_multisample_layout[] = {
[ISL_MSAA_LAYOUT_NONE] = MSFMT_MSS,
[ISL_MSAA_LAYOUT_INTERLEAVED] = MSFMT_DEPTH_STENCIL,
[ISL_MSAA_LAYOUT_ARRAY] = MSFMT_MSS,
};
+#endif
#if GEN_GEN >= 9
static const uint32_t isl_to_gen_aux_mode[] = {
@@ -130,7 +132,7 @@ get_surftype(enum isl_surf_dim dim, isl_surf_usage_flags_t usage)
* hardware. Note that this does NOT give you the actual hardware enum values
* but an index into the isl_to_gen_[hv]align arrays above.
*/
-static struct isl_extent3d
+static inline struct isl_extent3d
get_image_alignment(const struct isl_surf *surf)
{
if (GEN_GEN >= 9) {
@@ -217,6 +219,23 @@ isl_genX(surf_fill_state_s)(const struct isl_device *dev, void *state,
s.Width = info->surf->logical_level0_px.width - 1;
s.Height = info->surf->logical_level0_px.height - 1;
+ /* In the gen6 PRM Volume 1 Part 1: Graphics Core, Section 7.18.3.7.1
+ * (Surface Arrays For all surfaces other than separate stencil buffer):
+ *
+ * "[DevSNB] Errata: Sampler MSAA Qpitch will be 4 greater than the value
+ * calculated in the equation above , for every other odd Surface Height
+ * starting from 1 i.e. 1,5,9,13"
+ *
+ * Since this Qpitch errata only impacts the sampler, we have to adjust the
+ * input for the rendering surface to achieve the same qpitch. For the
+ * affected heights, we increment the height by 1 for the rendering
+ * surface.
+ */
+ if (GEN_GEN == 6 && (info->view->usage & ISL_SURF_USAGE_RENDER_TARGET_BIT) &&
+ info->surf->samples > 1 &&
+ (info->surf->logical_level0_px.height % 4) == 1)
+ s.Height++;
+
switch (s.SurfaceType) {
case SURFTYPE_1D:
case SURFTYPE_2D:
@@ -283,7 +302,9 @@ isl_genX(surf_fill_state_s)(const struct isl_device *dev, void *state,
unreachable("bad SurfaceType");
}
+#if GEN_GEN >= 7
s.SurfaceArray = info->surf->dim != ISL_SURF_DIM_3D;
+#endif
if (info->view->usage & ISL_SURF_USAGE_RENDER_TARGET_BIT) {
/* For render target surfaces, the hardware interprets field
@@ -311,9 +332,13 @@ isl_genX(surf_fill_state_s)(const struct isl_device *dev, void *state,
s.MipTailStartLOD = 15;
#endif
+#if GEN_GEN >= 6
const struct isl_extent3d image_align = get_image_alignment(info->surf);
s.SurfaceVerticalAlignment = isl_to_gen_valign[image_align.height];
+#if GEN_GEN >= 7
s.SurfaceHorizontalAlignment = isl_to_gen_halign[image_align.width];
+#endif
+#endif
if (info->surf->dim_layout == ISL_DIM_LAYOUT_GEN9_1D) {
/* For gen9 1-D textures, surface pitch is ignored */
@@ -356,9 +381,13 @@ isl_genX(surf_fill_state_s)(const struct isl_device *dev, void *state,
#endif
}
+#if GEN_GEN >= 6
+ s.NumberofMultisamples = ffs(info->surf->samples) - 1;
+#if GEN_GEN >= 7
s.MultisampledSurfaceStorageFormat =
isl_to_gen_multisample_layout[info->surf->msaa_layout];
- s.NumberofMultisamples = ffs(info->surf->samples) - 1;
+#endif
+#endif
#if (GEN_GEN >= 8 || GEN_IS_HASWELL)
s.ShaderChannelSelectRed = info->view->channel_select[0];
@@ -368,7 +397,10 @@ isl_genX(surf_fill_state_s)(const struct isl_device *dev, void *state,
#endif
s.SurfaceBaseAddress = info->address;
+
+#if GEN_GEN >= 6
s.MOCS = info->mocs;
+#endif
#if GEN_GEN >= 7
if (info->aux_surf && info->aux_usage != ISL_AUX_USAGE_NONE) {
@@ -480,15 +512,31 @@ isl_genX(buffer_fill_state_s)(void *state,
struct GENX(RENDER_SURFACE_STATE) s = { 0, };
s.SurfaceType = SURFTYPE_BUFFER;
- s.SurfaceArray = false;
s.SurfaceFormat = info->format;
+
+#if GEN_GEN >= 6
s.SurfaceVerticalAlignment = isl_to_gen_valign[4];
+#if GEN_GEN >= 7
s.SurfaceHorizontalAlignment = isl_to_gen_halign[4];
+ s.SurfaceArray = false;
+#endif
+#endif
+
+#if GEN_GEN >= 7
s.Height = ((num_elements - 1) >> 7) & 0x3fff;
s.Width = (num_elements - 1) & 0x7f;
s.Depth = ((num_elements - 1) >> 21) & 0x3ff;
+#else
+ s.Height = ((num_elements - 1) >> 7) & 0x1fff;
+ s.Width = (num_elements - 1) & 0x7f;
+ s.Depth = ((num_elements - 1) >> 20) & 0x7f;
+#endif
+
s.SurfacePitch = info->stride - 1;
+
+#if GEN_GEN >= 6
s.NumberofMultisamples = MULTISAMPLECOUNT_1;
+#endif
#if (GEN_GEN >= 8)
s.TileMode = LINEAR;
@@ -503,7 +551,9 @@ isl_genX(buffer_fill_state_s)(void *state,
#endif
s.SurfaceBaseAddress = info->address;
+#if GEN_GEN >= 6
s.MOCS = info->mocs;
+#endif
#if (GEN_GEN >= 8 || GEN_IS_HASWELL)
s.ShaderChannelSelectRed = SCS_RED;