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authorNanley Chery <[email protected]>2017-03-07 11:17:05 -0800
committerAndres Gomez <[email protected]>2017-03-29 19:13:17 +0300
commite504ecb6c6963a9692b25b048b6b185f821ef939 (patch)
treefd32c663f0caca86d5f0f02049109a2bfdd702a0 /src/intel
parentd80b96f98010aec59b6f4ce9949a3909d3023c13 (diff)
intel: Correct the BDW surface state size
The PRMs state that this packet is 16 DWORDS long. Ensure that the last three DWORDS are zeroed as required by the hardware when allocating a null surface state. Cc: <[email protected]> Signed-off-by: Nanley Chery <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Anuj Phogat <[email protected]> (cherry picked from commit 7c50f9903f58ef04ff393505a383d06f499f1fdc)
Diffstat (limited to 'src/intel')
-rw-r--r--src/intel/isl/isl.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/intel/isl/isl.c b/src/intel/isl/isl.c
index 82ab68dc65a..59d8b3a49a2 100644
--- a/src/intel/isl/isl.c
+++ b/src/intel/isl/isl.c
@@ -56,7 +56,7 @@ static const struct {
[5] = {24, 32, 4},
[6] = {24, 32, 4},
[7] = {32, 32, 4, 24},
- [8] = {52, 64, 32, 40},
+ [8] = {64, 64, 32, 40},
[9] = {64, 64, 32, 40},
};