diff options
| author | Kenneth Graunke <[email protected]> | 2018-01-02 14:26:41 -0800 |
|---|---|---|
| committer | Kenneth Graunke <[email protected]> | 2018-01-09 10:13:33 -0800 |
| commit | 8eadc2fb8fe395ea0a8202217bd5545978962d1d (patch) | |
| tree | 7797386a6773339af84f0ff951b446f73e013de4 /src/intel | |
| parent | 5e7d06fcb0c1f11373ff940670744486a467af93 (diff) | |
intel: Apply Geminilake "Barrier Mode" workaround.
Apparently, Geminilake requires you to whack a chicken bit to select
either compute or tessellation mode for barriers. The recommendation
is to switch between them at PIPELINE_SELECT time.
We may not need to do this all the time, but I don't know that it hurts
either. PIPELINE_SELECT is already a pretty giant stall.
This appears to fix hangs in tessellation control shaders with barriers
on Geminilake. Note that this requires a corresponding kernel change,
drm/i915: Whitelist SLICE_COMMON_ECO_CHICKEN1 on Geminilake.
in order for the register write to actually happen. Without an updated
kernel, this register write will be noop'd and the fix will not work.
Reviewed-by: Rafael Antognolli <[email protected]>
Diffstat (limited to 'src/intel')
| -rw-r--r-- | src/intel/genxml/gen9.xml | 8 | ||||
| -rw-r--r-- | src/intel/vulkan/genX_cmd_buffer.c | 21 |
2 files changed, 29 insertions, 0 deletions
diff --git a/src/intel/genxml/gen9.xml b/src/intel/genxml/gen9.xml index 1422463693d..f07ed748ac7 100644 --- a/src/intel/genxml/gen9.xml +++ b/src/intel/genxml/gen9.xml @@ -3710,6 +3710,14 @@ <field name="Color Compression Disable Mask" start="31" end="31" type="bool"/> </register> + <register name="SLICE_COMMON_ECO_CHICKEN1" length="1" num="0x731c"> + <field name="GLK Barrier Mode" start="7" end="7" type="uint"> + <value name="GLK_BARRIER_MODE_GPGPU" value="0"/> + <value name="GLK_BARRIER_MODE_3D_HULL" value="1"/> + </field> + <field name="GLK Barrier Mode Mask" start="23" end="23" type="bool"/> + </register> + <register name="GFX_ARB_ERROR_RPT" length="1" num="0x40a0"> <field name="TLB Page Fault Error" start="0" end="0" type="bool"/> <field name="RSTRM PAVP Read Invalid" start="1" end="1" type="bool"/> diff --git a/src/intel/vulkan/genX_cmd_buffer.c b/src/intel/vulkan/genX_cmd_buffer.c index b7253d52513..ac95f3ad05a 100644 --- a/src/intel/vulkan/genX_cmd_buffer.c +++ b/src/intel/vulkan/genX_cmd_buffer.c @@ -2734,6 +2734,8 @@ static void genX(flush_pipeline_select)(struct anv_cmd_buffer *cmd_buffer, uint32_t pipeline) { + UNUSED const struct gen_device_info *devinfo = &cmd_buffer->device->info; + if (cmd_buffer->state.current_pipeline == pipeline) return; @@ -2784,6 +2786,25 @@ genX(flush_pipeline_select)(struct anv_cmd_buffer *cmd_buffer, ps.PipelineSelection = pipeline; } +#if GEN_GEN == 9 + if (devinfo->is_geminilake) { + /* Project: DevGLK + * + * "This chicken bit works around a hardware issue with barrier logic + * encountered when switching between GPGPU and 3D pipelines. To + * workaround the issue, this mode bit should be set after a pipeline + * is selected." + */ + uint32_t scec; + anv_pack_struct(&scec, GENX(SLICE_COMMON_ECO_CHICKEN1), + .GLKBarrierMode = + pipeline == GPGPU ? GLK_BARRIER_MODE_GPGPU + : GLK_BARRIER_MODE_3D_HULL, + .GLKBarrierModeMask = 1); + emit_lri(&cmd_buffer->batch, GENX(SLICE_COMMON_ECO_CHICKEN1_num), scec); + } +#endif + cmd_buffer->state.current_pipeline = pipeline; } |