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authorJason Ekstrand <[email protected]>2017-05-30 09:53:43 -0700
committerJason Ekstrand <[email protected]>2017-06-01 15:34:01 -0700
commit1a22c4c960b80f7f7d075b362cf78544e235a861 (patch)
tree492dab9da02a640a7da39961afc84645a8fec13b /src/intel
parentd065a9540cb4c4f064f695194e35c8c1c3d2b419 (diff)
intel/blorp: Handle gen6 stencil/HiZ offsets in the back-end
Reviewed-by: Topi Pohjolainen <[email protected]>
Diffstat (limited to 'src/intel')
-rw-r--r--src/intel/blorp/blorp_genX_exec.h32
1 files changed, 30 insertions, 2 deletions
diff --git a/src/intel/blorp/blorp_genX_exec.h b/src/intel/blorp/blorp_genX_exec.h
index 8b9b8d27755..59c1d364947 100644
--- a/src/intel/blorp/blorp_genX_exec.h
+++ b/src/intel/blorp/blorp_genX_exec.h
@@ -1384,9 +1384,23 @@ blorp_emit_depth_stencil_config(struct blorp_batch *batch,
if (info.hiz_usage == ISL_AUX_USAGE_HIZ) {
info.hiz_surf = &params->depth.aux_surf;
+ struct blorp_address hiz_address = params->depth.aux_addr;
+#if GEN_GEN == 6
+ /* Sandy bridge hardware does not technically support mipmapped HiZ.
+ * However, we have a special layout that allows us to make it work
+ * anyway by manually offsetting to the specified miplevel.
+ */
+ assert(info.hiz_surf->dim_layout == ISL_DIM_LAYOUT_GEN6_STENCIL_HIZ);
+ uint32_t offset_B;
+ isl_surf_get_image_offset_B_tile_sa(info.hiz_surf,
+ info.view->base_level, 0, 0,
+ &offset_B, NULL, NULL);
+ hiz_address.offset += offset_B;
+#endif
+
info.hiz_address =
blorp_emit_reloc(batch, dw + isl_dev->ds.hiz_offset / 4,
- params->depth.aux_addr, 0);
+ hiz_address, 0);
info.depth_clear_value = params->depth.clear_color.u32[0];
}
@@ -1395,9 +1409,23 @@ blorp_emit_depth_stencil_config(struct blorp_batch *batch,
if (params->stencil.enabled) {
info.stencil_surf = &params->stencil.surf;
+ struct blorp_address stencil_address = params->stencil.addr;
+#if GEN_GEN == 6
+ /* Sandy bridge hardware does not technically support mipmapped stencil.
+ * However, we have a special layout that allows us to make it work
+ * anyway by manually offsetting to the specified miplevel.
+ */
+ assert(info.stencil_surf->dim_layout == ISL_DIM_LAYOUT_GEN6_STENCIL_HIZ);
+ uint32_t offset_B;
+ isl_surf_get_image_offset_B_tile_sa(info.stencil_surf,
+ info.view->base_level, 0, 0,
+ &offset_B, NULL, NULL);
+ stencil_address.offset += offset_B;
+#endif
+
info.stencil_address =
blorp_emit_reloc(batch, dw + isl_dev->ds.stencil_offset / 4,
- params->stencil.addr, 0);
+ stencil_address, 0);
}
isl_emit_depth_stencil_hiz_s(isl_dev, dw, &info);