diff options
| author | Kenneth Graunke <[email protected]> | 2019-08-26 15:21:40 -0700 |
|---|---|---|
| committer | Kenneth Graunke <[email protected]> | 2019-08-27 14:20:07 -0700 |
| commit | c8c9c4868429f98e77f782637568e9eed2dd33f9 (patch) | |
| tree | 76e5d8e1d927b7bc872a4979a2a4df65d6d882cd /src/intel | |
| parent | 360cf3c4b05679709574ef4d20b5097b0fd0be82 (diff) | |
intel/compiler: Fix src0/desc setter ordering
src0 vstride and type overlap with bits of the extended descriptor.
brw_set_desc() also sets the extended descriptor to 0. So by setting
the descriptor, then setting src0, we were accidentally setting a bunch
of extended descriptor bits unintentionally.
When using this infrastructure for framebuffer writes (in a future
patch), this ended up setting the extended descriptor bit 20, which is
"Null Render Target" on Icelake, causing nothing to be written to the
framebuffer.
Reviewed-by: Jason Ekstrand <[email protected]>
Diffstat (limited to 'src/intel')
| -rw-r--r-- | src/intel/compiler/brw_eu_emit.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/intel/compiler/brw_eu_emit.c b/src/intel/compiler/brw_eu_emit.c index 60761e83c62..1fb5156937c 100644 --- a/src/intel/compiler/brw_eu_emit.c +++ b/src/intel/compiler/brw_eu_emit.c @@ -2525,8 +2525,8 @@ brw_send_indirect_message(struct brw_codegen *p, if (desc.file == BRW_IMMEDIATE_VALUE) { send = next_insn(p, BRW_OPCODE_SEND); + brw_set_src0(p, send, retype(payload, BRW_REGISTER_TYPE_UD)); brw_set_desc(p, send, desc.ud | desc_imm); - } else { struct brw_reg addr = retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD); @@ -2545,11 +2545,11 @@ brw_send_indirect_message(struct brw_codegen *p, brw_pop_insn_state(p); send = next_insn(p, BRW_OPCODE_SEND); + brw_set_src0(p, send, retype(payload, BRW_REGISTER_TYPE_UD)); brw_set_src1(p, send, addr); } brw_set_dest(p, send, dst); - brw_set_src0(p, send, retype(payload, BRW_REGISTER_TYPE_UD)); brw_inst_set_sfid(devinfo, send, sfid); brw_inst_set_eot(devinfo, send, eot); } |