diff options
| author | Lionel Landwerlin <[email protected]> | 2020-01-15 00:05:30 +0200 |
|---|---|---|
| committer | Lionel Landwerlin <[email protected]> | 2020-01-15 11:14:43 +0200 |
| commit | a01410549807cc4db6fc5fe10c47649cde1fe3fc (patch) | |
| tree | ab76cd9d5352e71076eaed018a75a363832602a7 /src/intel | |
| parent | fce28a7341e670698f16e57907335653a9ec8261 (diff) | |
anv: fix pipeline switch back for non pipelined states
Setting state base address can happen even before pipeline is
selected. Also we must ensure it is set to 3D for Gen12, we can't
switch back to an invalid pipeline value (UINT32_MAX).
v2: Reuse helpers (Jason)
Signed-off-by: Lionel Landwerlin <[email protected]>
Fixes: b34422db5e66 ("anv: Implement Gen12 workaround for non pipelined state")
Reviewed-by: Jason Ekstrand <[email protected]>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3396>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3396>
Diffstat (limited to 'src/intel')
| -rw-r--r-- | src/intel/vulkan/genX_cmd_buffer.c | 21 |
1 files changed, 8 insertions, 13 deletions
diff --git a/src/intel/vulkan/genX_cmd_buffer.c b/src/intel/vulkan/genX_cmd_buffer.c index addd5e80b49..a573a79fe27 100644 --- a/src/intel/vulkan/genX_cmd_buffer.c +++ b/src/intel/vulkan/genX_cmd_buffer.c @@ -40,6 +40,9 @@ #define __gen_address_offset anv_address_add #include "common/gen_mi_builder.h" +static void genX(flush_pipeline_select)(struct anv_cmd_buffer *cmd_buffer, + uint32_t pipeline); + static void emit_lri(struct anv_batch *batch, uint32_t reg, uint32_t imm) { @@ -82,12 +85,8 @@ genX(cmd_buffer_emit_state_base_address)(struct anv_cmd_buffer *cmd_buffer) * Workaround the non pipelined state not applying in MEDIA/GPGPU pipeline * mode by putting the pipeline temporarily in 3D mode. */ - if (cmd_buffer->state.current_pipeline != _3D) { - anv_batch_emit(&cmd_buffer->batch, GENX(PIPELINE_SELECT), ps) { - ps.MaskBits = 3; - ps.PipelineSelection = _3D; - } - } + uint32_t gen12_wa_pipeline = cmd_buffer->state.current_pipeline; + genX(flush_pipeline_select_3d)(cmd_buffer); #endif anv_batch_emit(&cmd_buffer->batch, GENX(STATE_BASE_ADDRESS), sba) { @@ -172,14 +171,10 @@ genX(cmd_buffer_emit_state_base_address)(struct anv_cmd_buffer *cmd_buffer) #if GEN_GEN == 12 /* GEN:BUG:1607854226: * - * Put the pipeline back into compute mode. + * Put the pipeline back into its current mode. */ - if (cmd_buffer->state.current_pipeline != _3D) { - anv_batch_emit(&cmd_buffer->batch, GENX(PIPELINE_SELECT), ps) { - ps.MaskBits = 3; - ps.PipelineSelection = cmd_buffer->state.current_pipeline; - } - } + if (gen12_wa_pipeline != UINT32_MAX) + genX(flush_pipeline_select)(cmd_buffer, gen12_wa_pipeline); #endif /* After re-setting the surface state base address, we have to do some |