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authorJason Ekstrand <[email protected]>2018-01-19 15:14:37 -0800
committerJason Ekstrand <[email protected]>2018-02-08 16:35:31 -0800
commit8f20cf166ed434092242dba05a09f682df3028d8 (patch)
tree72d5ee16653f7b397bcd52a8b15afe9fa6fbcd79 /src/intel
parent1e941a05283b6873d2501f17944e545f6c76166f (diff)
intel/blorp: Use isl_aux_op instead of blorp_hiz_op
Reviewed-by: Topi Pohjolainen <[email protected]> Reviewed-by: Nanley Chery <[email protected]>
Diffstat (limited to 'src/intel')
-rw-r--r--src/intel/blorp/blorp.c2
-rw-r--r--src/intel/blorp/blorp.h19
-rw-r--r--src/intel/blorp/blorp_clear.c2
-rw-r--r--src/intel/blorp/blorp_genX_exec.h39
-rw-r--r--src/intel/blorp/blorp_priv.h2
-rw-r--r--src/intel/vulkan/anv_blorp.c15
6 files changed, 26 insertions, 53 deletions
diff --git a/src/intel/blorp/blorp.c b/src/intel/blorp/blorp.c
index 52675ec4ac5..e348cafb2e5 100644
--- a/src/intel/blorp/blorp.c
+++ b/src/intel/blorp/blorp.c
@@ -295,7 +295,7 @@ blorp_ensure_sf_program(struct blorp_context *blorp,
void
blorp_hiz_op(struct blorp_batch *batch, struct blorp_surf *surf,
uint32_t level, uint32_t start_layer, uint32_t num_layers,
- enum blorp_hiz_op op)
+ enum isl_aux_op op)
{
struct blorp_params params;
blorp_params_init(&params);
diff --git a/src/intel/blorp/blorp.h b/src/intel/blorp/blorp.h
index f1be12ba91e..ce3762c42fa 100644
--- a/src/intel/blorp/blorp.h
+++ b/src/intel/blorp/blorp.h
@@ -207,27 +207,10 @@ blorp_mcs_partial_resolve(struct blorp_batch *batch,
enum isl_format format,
uint32_t start_layer, uint32_t num_layers);
-/**
- * For an overview of the HiZ operations, see the following sections of the
- * Sandy Bridge PRM, Volume 1, Part2:
- * - 7.5.3.1 Depth Buffer Clear
- * - 7.5.3.2 Depth Buffer Resolve
- * - 7.5.3.3 Hierarchical Depth Buffer Resolve
- *
- * Of these, two get entered in the resolve map as needing to be done to the
- * buffer: depth resolve and hiz resolve.
- */
-enum blorp_hiz_op {
- BLORP_HIZ_OP_NONE,
- BLORP_HIZ_OP_DEPTH_CLEAR,
- BLORP_HIZ_OP_DEPTH_RESOLVE,
- BLORP_HIZ_OP_HIZ_RESOLVE,
-};
-
void
blorp_hiz_op(struct blorp_batch *batch, struct blorp_surf *surf,
uint32_t level, uint32_t start_layer, uint32_t num_layers,
- enum blorp_hiz_op op);
+ enum isl_aux_op op);
#ifdef __cplusplus
} /* end extern "C" */
diff --git a/src/intel/blorp/blorp_clear.c b/src/intel/blorp/blorp_clear.c
index d205e5becae..421a6c5d345 100644
--- a/src/intel/blorp/blorp_clear.c
+++ b/src/intel/blorp/blorp_clear.c
@@ -630,7 +630,7 @@ blorp_gen8_hiz_clear_attachments(struct blorp_batch *batch,
struct blorp_params params;
blorp_params_init(&params);
params.num_layers = 1;
- params.hiz_op = BLORP_HIZ_OP_DEPTH_CLEAR;
+ params.hiz_op = ISL_AUX_OP_FAST_CLEAR;
params.x0 = x0;
params.y0 = y0;
params.x1 = x1;
diff --git a/src/intel/blorp/blorp_genX_exec.h b/src/intel/blorp/blorp_genX_exec.h
index 8d007b818ad..5e1312aa305 100644
--- a/src/intel/blorp/blorp_genX_exec.h
+++ b/src/intel/blorp/blorp_genX_exec.h
@@ -787,16 +787,16 @@ blorp_emit_ps_config(struct blorp_batch *batch,
blorp_emit(batch, GENX(3DSTATE_WM), wm) {
switch (params->hiz_op) {
- case BLORP_HIZ_OP_DEPTH_CLEAR:
+ case ISL_AUX_OP_FAST_CLEAR:
wm.DepthBufferClear = true;
break;
- case BLORP_HIZ_OP_DEPTH_RESOLVE:
+ case ISL_AUX_OP_FULL_RESOLVE:
wm.DepthBufferResolveEnable = true;
break;
- case BLORP_HIZ_OP_HIZ_RESOLVE:
+ case ISL_AUX_OP_AMBIGUATE:
wm.HierarchicalDepthBufferResolveEnable = true;
break;
- case BLORP_HIZ_OP_NONE:
+ case ISL_AUX_OP_NONE:
break;
default:
unreachable("not reached");
@@ -872,16 +872,16 @@ blorp_emit_ps_config(struct blorp_batch *batch,
batch->blorp->isl_dev->info->max_wm_threads - 1;
switch (params->hiz_op) {
- case BLORP_HIZ_OP_DEPTH_CLEAR:
+ case ISL_AUX_OP_FAST_CLEAR:
wm.DepthBufferClear = true;
break;
- case BLORP_HIZ_OP_DEPTH_RESOLVE:
+ case ISL_AUX_OP_FULL_RESOLVE:
wm.DepthBufferResolveEnable = true;
break;
- case BLORP_HIZ_OP_HIZ_RESOLVE:
+ case ISL_AUX_OP_AMBIGUATE:
wm.HierarchicalDepthBufferResolveEnable = true;
break;
- case BLORP_HIZ_OP_NONE:
+ case ISL_AUX_OP_NONE:
break;
default:
unreachable("not reached");
@@ -1014,7 +1014,7 @@ blorp_emit_depth_stencil_state(struct blorp_batch *batch,
ds.DepthBufferWriteEnable = true;
switch (params->hiz_op) {
- case BLORP_HIZ_OP_NONE:
+ case ISL_AUX_OP_NONE:
ds.DepthTestEnable = true;
ds.DepthTestFunction = COMPAREFUNCTION_ALWAYS;
break;
@@ -1024,15 +1024,17 @@ blorp_emit_depth_stencil_state(struct blorp_batch *batch,
* - 7.5.3.2 Depth Buffer Resolve
* - 7.5.3.3 Hierarchical Depth Buffer Resolve
*/
- case BLORP_HIZ_OP_DEPTH_RESOLVE:
+ case ISL_AUX_OP_FULL_RESOLVE:
ds.DepthTestEnable = true;
ds.DepthTestFunction = COMPAREFUNCTION_NEVER;
break;
- case BLORP_HIZ_OP_DEPTH_CLEAR:
- case BLORP_HIZ_OP_HIZ_RESOLVE:
+ case ISL_AUX_OP_FAST_CLEAR:
+ case ISL_AUX_OP_AMBIGUATE:
ds.DepthTestEnable = false;
break;
+ case ISL_AUX_OP_PARTIAL_RESOLVE:
+ unreachable("Invalid HIZ op");
}
}
@@ -1522,7 +1524,7 @@ blorp_emit_gen8_hiz_op(struct blorp_batch *batch,
* requested.
*/
if (params->stencil.enabled)
- assert(params->hiz_op == BLORP_HIZ_OP_DEPTH_CLEAR);
+ assert(params->hiz_op == ISL_AUX_OP_FAST_CLEAR);
/* From the BDW PRM Volume 2, 3DSTATE_WM_HZ_OP:
*
@@ -1547,21 +1549,22 @@ blorp_emit_gen8_hiz_op(struct blorp_batch *batch,
blorp_emit(batch, GENX(3DSTATE_WM_HZ_OP), hzp) {
switch (params->hiz_op) {
- case BLORP_HIZ_OP_DEPTH_CLEAR:
+ case ISL_AUX_OP_FAST_CLEAR:
hzp.StencilBufferClearEnable = params->stencil.enabled;
hzp.DepthBufferClearEnable = params->depth.enabled;
hzp.StencilClearValue = params->stencil_ref;
hzp.FullSurfaceDepthandStencilClear = params->full_surface_hiz_op;
break;
- case BLORP_HIZ_OP_DEPTH_RESOLVE:
+ case ISL_AUX_OP_FULL_RESOLVE:
assert(params->full_surface_hiz_op);
hzp.DepthBufferResolveEnable = true;
break;
- case BLORP_HIZ_OP_HIZ_RESOLVE:
+ case ISL_AUX_OP_AMBIGUATE:
assert(params->full_surface_hiz_op);
hzp.HierarchicalDepthBufferResolveEnable = true;
break;
- case BLORP_HIZ_OP_NONE:
+ case ISL_AUX_OP_PARTIAL_RESOLVE:
+ case ISL_AUX_OP_NONE:
unreachable("Invalid HIZ op");
}
@@ -1605,7 +1608,7 @@ static void
blorp_exec(struct blorp_batch *batch, const struct blorp_params *params)
{
#if GEN_GEN >= 8
- if (params->hiz_op != BLORP_HIZ_OP_NONE) {
+ if (params->hiz_op != ISL_AUX_OP_NONE) {
blorp_emit_gen8_hiz_op(batch, params);
return;
}
diff --git a/src/intel/blorp/blorp_priv.h b/src/intel/blorp/blorp_priv.h
index ef3fc6d378e..3fd2203959f 100644
--- a/src/intel/blorp/blorp_priv.h
+++ b/src/intel/blorp/blorp_priv.h
@@ -190,7 +190,7 @@ struct blorp_params
uint32_t depth_format;
struct brw_blorp_surface_info src;
struct brw_blorp_surface_info dst;
- enum blorp_hiz_op hiz_op;
+ enum isl_aux_op hiz_op;
bool full_surface_hiz_op;
enum isl_aux_op fast_clear_op;
bool color_write_disable[4];
diff --git a/src/intel/vulkan/anv_blorp.c b/src/intel/vulkan/anv_blorp.c
index 7d0ded3423c..d38b343671f 100644
--- a/src/intel/vulkan/anv_blorp.c
+++ b/src/intel/vulkan/anv_blorp.c
@@ -1618,18 +1618,6 @@ anv_image_copy_to_shadow(struct anv_cmd_buffer *cmd_buffer,
blorp_batch_finish(&batch);
}
-static enum blorp_hiz_op
-isl_to_blorp_hiz_op(enum isl_aux_op isl_op)
-{
- switch (isl_op) {
- case ISL_AUX_OP_FAST_CLEAR: return BLORP_HIZ_OP_DEPTH_CLEAR;
- case ISL_AUX_OP_FULL_RESOLVE: return BLORP_HIZ_OP_DEPTH_RESOLVE;
- case ISL_AUX_OP_AMBIGUATE: return BLORP_HIZ_OP_HIZ_RESOLVE;
- default:
- unreachable("Unsupported HiZ aux op");
- }
-}
-
void
anv_image_hiz_op(struct anv_cmd_buffer *cmd_buffer,
const struct anv_image *image,
@@ -1651,8 +1639,7 @@ anv_image_hiz_op(struct anv_cmd_buffer *cmd_buffer,
ISL_AUX_USAGE_HIZ, &surf);
surf.clear_color.f32[0] = ANV_HZ_FC_VAL;
- blorp_hiz_op(&batch, &surf, level, base_layer, layer_count,
- isl_to_blorp_hiz_op(hiz_op));
+ blorp_hiz_op(&batch, &surf, level, base_layer, layer_count, hiz_op);
blorp_batch_finish(&batch);
}