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authorSamuel Iglesias Gonsálvez <[email protected]>2019-02-12 15:43:10 +0100
committerAndres Gomez <[email protected]>2019-09-17 23:39:18 +0300
commit7580707345b7df0f262935c30b43bde16d297e39 (patch)
tree9652120d350202eebe9253f0bc9c829d0b057da6 /src/intel
parent0ac07c7ca7207f3f1388c0450b456ecc578d9c5b (diff)
nir: mind rounding mode on fadd, fsub, fmul and fma opcodes
According to Vulkan spec, the new execution modes affect only correctly rounded SPIR-V instructions, which includes fadd, fsub and fmul. v2: - Fix fmul, fsub and fadd round-to-zero definitions, they should use auxiliary functions to calculate the proper value because Mesa uses round-to-nearest-even rounding mode by default (Connor). v3: - Do an actual fused multiply-add at ffma (Connor). v4: - Simplify fadd and fmul for bit sizes < 64 (Connor). - Do not use double ffma for 32 bits float (Connor). Signed-off-by: Samuel Iglesias Gonsálvez <[email protected]> Signed-off-by: Andres Gomez <[email protected]> Reviewed-by: Connor Abbott <[email protected]> [v3]
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