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authorSagar Ghuge <[email protected]>2019-05-30 14:14:52 -0700
committerSagar Ghuge <[email protected]>2019-07-01 10:14:22 -0700
commit1e92e83856b1ef8a827a63359d59ed7883ed4994 (patch)
treec76992caeab4ea506d2eee173846c90ad01ff97a /src/intel
parent80117117bda10144df57614e718b8c19ee7afdf4 (diff)
intel/compiler: Emit ROR and ROL instruction
v2: Reorder patch (Matt Turner) Signed-off-by: Sagar Ghuge <[email protected]> Reviewed-by: Matt Turner <[email protected]>
Diffstat (limited to 'src/intel')
-rw-r--r--src/intel/compiler/brw_compiler.c2
-rw-r--r--src/intel/compiler/brw_fs_nir.cpp7
2 files changed, 9 insertions, 0 deletions
diff --git a/src/intel/compiler/brw_compiler.c b/src/intel/compiler/brw_compiler.c
index 550b2e7d756..aacd9f2aca4 100644
--- a/src/intel/compiler/brw_compiler.c
+++ b/src/intel/compiler/brw_compiler.c
@@ -182,6 +182,8 @@ brw_compiler_create(void *mem_ctx, const struct gen_device_info *devinfo)
nir_options->lower_ffma = devinfo->gen < 6;
nir_options->lower_flrp32 = devinfo->gen < 6 || devinfo->gen >= 11;
+ nir_options->lower_rotate = devinfo->gen < 11;
+
nir_options->lower_int64_options = int64_options;
nir_options->lower_doubles_options = fp64_options;
compiler->glsl_compiler_options[i].NirOptions = nir_options;
diff --git a/src/intel/compiler/brw_fs_nir.cpp b/src/intel/compiler/brw_fs_nir.cpp
index b9d42b6e26e..125bdc72032 100644
--- a/src/intel/compiler/brw_fs_nir.cpp
+++ b/src/intel/compiler/brw_fs_nir.cpp
@@ -1768,6 +1768,13 @@ fs_visitor::nir_emit_alu(const fs_builder &bld, nir_alu_instr *instr,
bld.SHR(result, op[0], op[1]);
break;
+ case nir_op_urol:
+ bld.ROL(result, op[0], op[1]);
+ break;
+ case nir_op_uror:
+ bld.ROR(result, op[0], op[1]);
+ break;
+
case nir_op_pack_half_2x16_split:
bld.emit(FS_OPCODE_PACK_HALF_2x16_SPLIT, result, op[0], op[1]);
break;