diff options
| author | Jason Ekstrand <[email protected]> | 2017-05-12 22:52:55 -0700 |
|---|---|---|
| committer | Jason Ekstrand <[email protected]> | 2017-05-26 07:58:01 -0700 |
| commit | fa13ef285df887d31f7012a4f32a4ff46a5920dc (patch) | |
| tree | 039fddb6547484682c6ad1c7fca14fc7239ab74d /src/intel | |
| parent | 752d7af77a52898cebf5597def4fdd38b1d6303e (diff) | |
intel/blorp: Assert that no one tries to blit combined depth stencil
Reviewed-by: Topi Pohjolainen <[email protected]>
Diffstat (limited to 'src/intel')
| -rw-r--r-- | src/intel/blorp/blorp_blit.c | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/src/intel/blorp/blorp_blit.c b/src/intel/blorp/blorp_blit.c index fe24f1f4753..42e770367df 100644 --- a/src/intel/blorp/blorp_blit.c +++ b/src/intel/blorp/blorp_blit.c @@ -2042,6 +2042,12 @@ blorp_blit(struct blorp_batch *batch, struct blorp_params params; blorp_params_init(¶ms); + /* We cannot handle combined depth and stencil. */ + if (src_surf->surf->usage & ISL_SURF_USAGE_STENCIL_BIT) + assert(src_surf->surf->format == ISL_FORMAT_R8_UINT); + if (dst_surf->surf->usage & ISL_SURF_USAGE_STENCIL_BIT) + assert(dst_surf->surf->format == ISL_FORMAT_R8_UINT); + if (dst_surf->surf->usage & ISL_SURF_USAGE_STENCIL_BIT) { assert(src_surf->surf->usage & ISL_SURF_USAGE_STENCIL_BIT); /* Prior to Broadwell, we can't render to R8_UINT */ |