summaryrefslogtreecommitdiffstats
path: root/src/intel
diff options
context:
space:
mode:
authorJason Ekstrand <[email protected]>2017-06-02 10:36:04 -0700
committerJason Ekstrand <[email protected]>2017-06-14 18:15:05 -0700
commit96f9d4de7d7af65570c7d7b33666933bcb95aaa7 (patch)
tree1f650393df2075df79f0d4d1cf5bc23874c5ec71 /src/intel
parentee0e29dd0274038957af4ac62b5ffab8d2a25704 (diff)
intel/isl: Properly set SeparateStencilBufferEnable on gen5-6
On gen5-6, SeparateStencilBufferEnable and HierarchicalDepthBufferEnable come hand in hand and we have to set either both or neither. Reviewed-by: Samuel Iglesias Gonsálvez <[email protected]>
Diffstat (limited to 'src/intel')
-rw-r--r--src/intel/isl/isl_emit_depth_stencil.c13
1 files changed, 10 insertions, 3 deletions
diff --git a/src/intel/isl/isl_emit_depth_stencil.c b/src/intel/isl/isl_emit_depth_stencil.c
index 339da28bb84..0d541fd1ce5 100644
--- a/src/intel/isl/isl_emit_depth_stencil.c
+++ b/src/intel/isl/isl_emit_depth_stencil.c
@@ -113,6 +113,16 @@ isl_genX(emit_depth_stencil_hiz_s)(const struct isl_device *dev, void *batch,
#endif
}
+#if GEN_GEN == 5 || GEN_GEN == 6
+ const bool separate_stencil =
+ info->stencil_surf && info->stencil_surf->format == ISL_FORMAT_R8_UINT;
+ if (separate_stencil || info->hiz_usage == ISL_AUX_USAGE_HIZ) {
+ assert(ISL_DEV_USE_SEPARATE_STENCIL(dev));
+ db.SeparateStencilBufferEnable = true;
+ db.HierarchicalDepthBufferEnable = true;
+ }
+#endif
+
#if GEN_GEN >= 6
struct GENX(3DSTATE_STENCIL_BUFFER) sb = {
GENX(3DSTATE_STENCIL_BUFFER_header),
@@ -151,9 +161,6 @@ isl_genX(emit_depth_stencil_hiz_s)(const struct isl_device *dev, void *batch,
info->hiz_usage == ISL_AUX_USAGE_HIZ);
if (info->hiz_usage == ISL_AUX_USAGE_HIZ) {
db.HierarchicalDepthBufferEnable = true;
-#if GEN_GEN == 5 || GEN_GEN == 6
- db.SeparateStencilBufferEnable = true;
-#endif
hiz.SurfaceBaseAddress = info->hiz_address;
hiz.HierarchicalDepthBufferMOCS = info->mocs;