diff options
| author | Ian Romanick <[email protected]> | 2018-09-09 11:37:24 -0700 |
|---|---|---|
| committer | Ian Romanick <[email protected]> | 2019-04-18 12:37:48 -0700 |
| commit | 90430d04886227099253ed38de089aee0d713ec5 (patch) | |
| tree | bd5e77664ec5e75213ca8510243b4676646941a2 /src/intel | |
| parent | a90aa14f5a0514ed0caf2a6715bca44ce046fe72 (diff) | |
intel/fs: Eliminate dead code first
This simplifies the later patch "i965/fs: Generate better code for fsign
multiplied by a value".
shader-db results:
Broadwell and Skylake had similar results. (Skylake shown)
total cycles in shared programs: 372808735 -> 372809551 (<.01%)
cycles in affected programs: 1519520 -> 1520336 (0.05%)
helped: 243
HURT: 277
helped stats (abs) min: 1 max: 226 x̄: 34.05 x̃: 5
helped stats (rel) min: 0.01% max: 13.88% x̄: 1.46% x̃: 0.27%
HURT stats (abs) min: 1 max: 1810 x̄: 32.82 x̃: 5
HURT stats (rel) min: 0.01% max: 16.03% x̄: 1.56% x̃: 0.29%
95% mean confidence interval for cycles value: -7.18 10.32
95% mean confidence interval for cycles %-change: -0.17% 0.46%
Inconclusive result (value mean confidence interval includes 0).
Sandy Bridge, Haswell and Ivy Bridge had similar results. (Sandy Bridge shown)
total cycles in shared programs: 155091458 -> 155091109 (<.01%)
cycles in affected programs: 370797 -> 370448 (-0.09%)
helped: 24
HURT: 36
helped stats (abs) min: 1 max: 331 x̄: 103.17 x̃: 41
helped stats (rel) min: 0.02% max: 7.70% x̄: 2.07% x̃: 0.56%
HURT stats (abs) min: 1 max: 291 x̄: 59.08 x̃: 10
HURT stats (rel) min: 0.02% max: 5.29% x̄: 1.02% x̃: 0.15%
95% mean confidence interval for cycles value: -37.92 26.28
95% mean confidence interval for cycles %-change: -0.88% 0.45%
Inconclusive result (value mean confidence interval includes 0).
Iron Lake and GM45 had similar results. (GM45 shown)
total cycles in shared programs: 129133970 -> 129133978 (<.01%)
cycles in affected programs: 111966 -> 111974 (<.01%)
helped: 3
HURT: 1
helped stats (abs) min: 2 max: 4 x̄: 2.67 x̃: 2
helped stats (rel) min: <.01% max: <.01% x̄: <.01% x̃: <.01%
HURT stats (abs) min: 16 max: 16 x̄: 16.00 x̃: 16
HURT stats (rel) min: 0.07% max: 0.07% x̄: 0.07% x̃: 0.07%
95% mean confidence interval for cycles value: -12.93 16.93
95% mean confidence interval for cycles %-change: -0.05% 0.08%
Inconclusive result (value mean confidence interval includes 0).
Reviewed-by: Matt Turner <[email protected]>
Diffstat (limited to 'src/intel')
| -rw-r--r-- | src/intel/compiler/brw_fs.cpp | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/src/intel/compiler/brw_fs.cpp b/src/intel/compiler/brw_fs.cpp index ac01d137ce1..0a390e54354 100644 --- a/src/intel/compiler/brw_fs.cpp +++ b/src/intel/compiler/brw_fs.cpp @@ -6956,6 +6956,14 @@ fs_visitor::optimize() int iteration = 0; int pass_num = 0; + /* Before anything else, eliminate dead code. The results of some NIR + * instructions may effectively be calculated twice. Once when the + * instruction is encountered, and again when the user of that result is + * encountered. Wipe those away before algebraic optimizations and + * especially copy propagation can mix things up. + */ + OPT(dead_code_eliminate); + OPT(remove_extra_rounding_modes); do { |