diff options
| author | Sagar Ghuge <[email protected]> | 2019-03-29 14:04:03 -0700 |
|---|---|---|
| committer | Matt Turner <[email protected]> | 2019-05-07 14:33:48 -0700 |
| commit | 5d7a9e08114b0cda28656c6f4109dc6b4d98327f (patch) | |
| tree | ed3125dccf1e547174d5e237bde802be1fd1c10a /src/intel | |
| parent | 6c83a68ebc381b46a4226c0ebd060cbc0d3f8056 (diff) | |
intel/disasm: Disassemble immediate value properly for dim
On haswell, for dim instruction we encode immediate float value operand
into double float,
v2: Fix comment (Matt Turner)
Signed-off-by: Sagar Ghuge <[email protected]>
Reviewed-by: Matt Turner <[email protected]>
Diffstat (limited to 'src/intel')
| -rw-r--r-- | src/intel/compiler/brw_disasm.c | 15 |
1 files changed, 12 insertions, 3 deletions
diff --git a/src/intel/compiler/brw_disasm.c b/src/intel/compiler/brw_disasm.c index e1cc0f4925f..8b7047db00f 100644 --- a/src/intel/compiler/brw_disasm.c +++ b/src/intel/compiler/brw_disasm.c @@ -1339,9 +1339,18 @@ imm(FILE *file, const struct gen_device_info *devinfo, enum brw_reg_type type, format(file, "0x%08xV", brw_inst_imm_ud(devinfo, inst)); break; case BRW_REGISTER_TYPE_F: - format(file, "0x%"PRIx64"F", brw_inst_bits(inst, 127, 96)); - pad(file, 48); - format(file, " /* %-gF */", brw_inst_imm_f(devinfo, inst)); + /* The DIM instruction's src0 uses an F type but contains a + * 64-bit immediate + */ + if (brw_inst_opcode(devinfo, inst) == BRW_OPCODE_DIM) { + format(file, "0x%"PRIx64"F", brw_inst_bits(inst, 127, 64)); + pad(file, 48); + format(file, "/* %-gF */", brw_inst_imm_df(devinfo, inst)); + } else { + format(file, "0x%"PRIx64"F", brw_inst_bits(inst, 127, 96)); + pad(file, 48); + format(file, " /* %-gF */", brw_inst_imm_f(devinfo, inst)); + } break; case BRW_REGISTER_TYPE_DF: format(file, "0x%016"PRIx64"DF", brw_inst_bits(inst, 127, 64)); |