diff options
author | Nanley Chery <[email protected]> | 2019-04-29 12:59:35 -0700 |
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committer | Nanley Chery <[email protected]> | 2019-05-14 16:23:12 +0000 |
commit | 29a13eb71da11d432287f93fe319b5cf1edc1aae (patch) | |
tree | 0f3ed8519a4cedcd6fba39607a3034977fcee1ef /src/intel | |
parent | 942755bec4437c59b803ab3420e7e6d7ac7ce2a6 (diff) |
isl: Add restrictions to isl_surf_get_hiz_surf()
Import some restrictions from intel_tiling_supports_hiz() and
intel_miptree_supports_hiz().
Reviewed-by: Rafael Antognolli <[email protected]>
Diffstat (limited to 'src/intel')
-rw-r--r-- | src/intel/isl/isl.c | 25 |
1 files changed, 25 insertions, 0 deletions
diff --git a/src/intel/isl/isl.c b/src/intel/isl/isl.c index 65925f92c3f..2e33031cbbf 100644 --- a/src/intel/isl/isl.c +++ b/src/intel/isl/isl.c @@ -1607,6 +1607,31 @@ isl_surf_get_hiz_surf(const struct isl_device *dev, { assert(ISL_DEV_GEN(dev) >= 5 && ISL_DEV_USE_SEPARATE_STENCIL(dev)); + /* HiZ only works with Y-tiled depth buffers */ + if (!isl_tiling_is_any_y(surf->tiling)) + return false; + + /* On SNB+, compressed depth buffers cannot be interleaved with stencil. */ + switch (surf->format) { + case ISL_FORMAT_R24_UNORM_X8_TYPELESS: + if (isl_surf_usage_is_depth_and_stencil(surf->usage)) { + assert(ISL_DEV_GEN(dev) == 5); + unreachable("This should work, but is untested"); + } + /* Fall through */ + case ISL_FORMAT_R16_UNORM: + case ISL_FORMAT_R32_FLOAT: + break; + case ISL_FORMAT_R32_FLOAT_X8X24_TYPELESS: + if (ISL_DEV_GEN(dev) == 5) { + assert(isl_surf_usage_is_depth_and_stencil(surf->usage)); + unreachable("This should work, but is untested"); + } + /* Fall through */ + default: + return false; + } + /* Multisampled depth is always interleaved */ assert(surf->msaa_layout == ISL_MSAA_LAYOUT_NONE || surf->msaa_layout == ISL_MSAA_LAYOUT_INTERLEAVED); |