diff options
author | Jason Ekstrand <[email protected]> | 2015-04-08 02:41:33 -0700 |
---|---|---|
committer | Jason Ekstrand <[email protected]> | 2019-11-11 17:17:02 +0000 |
commit | a0999bc0493293a5cc1b66f914223ef1d830a925 (patch) | |
tree | 8601fa5ee0d818fc4a4fd1be56667537b57f144a /src/intel | |
parent | 83f04d80b0eda4a0eedebe183b3da09cf844c05c (diff) |
intel/fs: Add DWord scattered read/write opcodes
Reviewed-by: Caio Marcelo de Oliveira Filho <[email protected]>
Diffstat (limited to 'src/intel')
-rw-r--r-- | src/intel/compiler/brw_eu.h | 31 | ||||
-rw-r--r-- | src/intel/compiler/brw_eu_defines.h | 2 | ||||
-rw-r--r-- | src/intel/compiler/brw_fs.cpp | 25 | ||||
-rw-r--r-- | src/intel/compiler/brw_schedule_instructions.cpp | 2 | ||||
-rw-r--r-- | src/intel/compiler/brw_shader.cpp | 6 |
5 files changed, 66 insertions, 0 deletions
diff --git a/src/intel/compiler/brw_eu.h b/src/intel/compiler/brw_eu.h index c35725bfe2b..ce1368a7fd3 100644 --- a/src/intel/compiler/brw_eu.h +++ b/src/intel/compiler/brw_eu.h @@ -698,6 +698,37 @@ brw_dp_byte_scattered_rw_desc(const struct gen_device_info *devinfo, } static inline uint32_t +brw_dp_dword_scattered_rw_desc(const struct gen_device_info *devinfo, + unsigned exec_size, + bool write) +{ + assert(exec_size == 8 || exec_size == 16); + + unsigned msg_type; + if (write) { + if (devinfo->gen >= 6) { + msg_type = GEN6_DATAPORT_WRITE_MESSAGE_DWORD_SCATTERED_WRITE; + } else { + msg_type = BRW_DATAPORT_WRITE_MESSAGE_DWORD_SCATTERED_WRITE; + } + } else { + if (devinfo->gen >= 7) { + msg_type = GEN7_DATAPORT_DC_DWORD_SCATTERED_READ; + } else if (devinfo->gen > 4 || devinfo->is_g4x) { + msg_type = G45_DATAPORT_READ_MESSAGE_DWORD_SCATTERED_READ; + } else { + msg_type = BRW_DATAPORT_READ_MESSAGE_DWORD_SCATTERED_READ; + } + } + + const unsigned msg_control = + SET_BITS(1, 1, 1) | /* Legacy SIMD Mode */ + SET_BITS(exec_size == 16, 0, 0); + + return brw_dp_surface_desc(devinfo, msg_type, msg_control); +} + +static inline uint32_t brw_dp_a64_untyped_surface_rw_desc(const struct gen_device_info *devinfo, unsigned exec_size, /**< 0 for SIMD4x2 */ unsigned num_channels, diff --git a/src/intel/compiler/brw_eu_defines.h b/src/intel/compiler/brw_eu_defines.h index 8aa2c14fddf..d2d8d877e2c 100644 --- a/src/intel/compiler/brw_eu_defines.h +++ b/src/intel/compiler/brw_eu_defines.h @@ -446,6 +446,8 @@ enum opcode { */ SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL, SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL, + SHADER_OPCODE_DWORD_SCATTERED_READ_LOGICAL, + SHADER_OPCODE_DWORD_SCATTERED_WRITE_LOGICAL, /** * Memory fence messages. diff --git a/src/intel/compiler/brw_fs.cpp b/src/intel/compiler/brw_fs.cpp index 538745880c6..aedf8314c0d 100644 --- a/src/intel/compiler/brw_fs.cpp +++ b/src/intel/compiler/brw_fs.cpp @@ -925,6 +925,7 @@ fs_inst::components_read(unsigned i) const } case SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL: + case SHADER_OPCODE_DWORD_SCATTERED_READ_LOGICAL: /* Scattered logical opcodes use the following params: * src[0] Surface coordinates * src[1] Surface operation source (ignored for reads) @@ -937,6 +938,7 @@ fs_inst::components_read(unsigned i) const return i == SURFACE_LOGICAL_SRC_DATA ? 0 : 1; case SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL: + case SHADER_OPCODE_DWORD_SCATTERED_WRITE_LOGICAL: assert(src[SURFACE_LOGICAL_SRC_IMM_DIMS].file == IMM && src[SURFACE_LOGICAL_SRC_IMM_ARG].file == IMM); return 1; @@ -5462,6 +5464,13 @@ lower_surface_logical_send(const fs_builder &bld, fs_inst *inst) sfid = GEN7_SFID_DATAPORT_DATA_CACHE; break; + case SHADER_OPCODE_DWORD_SCATTERED_READ_LOGICAL: + case SHADER_OPCODE_DWORD_SCATTERED_WRITE_LOGICAL: + sfid = devinfo->gen >= 7 ? GEN7_SFID_DATAPORT_DATA_CACHE : + devinfo->gen >= 6 ? GEN6_SFID_DATAPORT_RENDER_CACHE : + BRW_DATAPORT_READ_TARGET_RENDER_CACHE; + break; + case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL: case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL: case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL: @@ -5515,6 +5524,18 @@ lower_surface_logical_send(const fs_builder &bld, fs_inst *inst) true /* write */); break; + case SHADER_OPCODE_DWORD_SCATTERED_READ_LOGICAL: + assert(arg.ud == 32); /* bit_size */ + desc = brw_dp_dword_scattered_rw_desc(devinfo, inst->exec_size, + false /* write */); + break; + + case SHADER_OPCODE_DWORD_SCATTERED_WRITE_LOGICAL: + assert(arg.ud == 32); /* bit_size */ + desc = brw_dp_dword_scattered_rw_desc(devinfo, inst->exec_size, + true /* write */); + break; + case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL: desc = brw_dp_untyped_atomic_desc(devinfo, inst->exec_size, arg.ud, /* atomic_op */ @@ -5874,6 +5895,8 @@ fs_visitor::lower_logical_sends() case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL: case SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL: case SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL: + case SHADER_OPCODE_DWORD_SCATTERED_READ_LOGICAL: + case SHADER_OPCODE_DWORD_SCATTERED_WRITE_LOGICAL: case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL: case SHADER_OPCODE_UNTYPED_ATOMIC_FLOAT_LOGICAL: case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL: @@ -6468,6 +6491,8 @@ get_lowered_simd_width(const struct gen_device_info *devinfo, case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL: case SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL: case SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL: + case SHADER_OPCODE_DWORD_SCATTERED_WRITE_LOGICAL: + case SHADER_OPCODE_DWORD_SCATTERED_READ_LOGICAL: return MIN2(16, inst->exec_size); case SHADER_OPCODE_A64_UNTYPED_WRITE_LOGICAL: diff --git a/src/intel/compiler/brw_schedule_instructions.cpp b/src/intel/compiler/brw_schedule_instructions.cpp index 08e89151e91..575693fc961 100644 --- a/src/intel/compiler/brw_schedule_instructions.cpp +++ b/src/intel/compiler/brw_schedule_instructions.cpp @@ -424,6 +424,8 @@ schedule_node::set_latency_gen7(bool is_haswell) case GEN7_SFID_DATAPORT_DATA_CACHE: switch ((inst->desc >> 14) & 0x1f) { + case GEN7_DATAPORT_DC_DWORD_SCATTERED_READ: + case GEN6_DATAPORT_WRITE_MESSAGE_DWORD_SCATTERED_WRITE: case HSW_DATAPORT_DC_PORT0_BYTE_SCATTERED_READ: case HSW_DATAPORT_DC_PORT0_BYTE_SCATTERED_WRITE: /* We have no data for this but assume it's roughly the same as diff --git a/src/intel/compiler/brw_shader.cpp b/src/intel/compiler/brw_shader.cpp index 94976a12c00..f95fcd99e67 100644 --- a/src/intel/compiler/brw_shader.cpp +++ b/src/intel/compiler/brw_shader.cpp @@ -331,6 +331,10 @@ brw_instruction_name(const struct gen_device_info *devinfo, enum opcode op) return "byte_scattered_read_logical"; case SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL: return "byte_scattered_write_logical"; + case SHADER_OPCODE_DWORD_SCATTERED_READ_LOGICAL: + return "dword_scattered_read_logical"; + case SHADER_OPCODE_DWORD_SCATTERED_WRITE_LOGICAL: + return "dword_scattered_write_logical"; case SHADER_OPCODE_LOAD_PAYLOAD: return "load_payload"; @@ -1055,6 +1059,7 @@ backend_instruction::has_side_effects() const case SHADER_OPCODE_A64_UNTYPED_ATOMIC_INT64_LOGICAL: case SHADER_OPCODE_A64_UNTYPED_ATOMIC_FLOAT_LOGICAL: case SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL: + case SHADER_OPCODE_DWORD_SCATTERED_WRITE_LOGICAL: case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL: case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL: case SHADER_OPCODE_MEMORY_FENCE: @@ -1088,6 +1093,7 @@ backend_instruction::is_volatile() const case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL: case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL: case SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL: + case SHADER_OPCODE_DWORD_SCATTERED_READ_LOGICAL: case SHADER_OPCODE_A64_UNTYPED_READ_LOGICAL: case SHADER_OPCODE_A64_BYTE_SCATTERED_READ_LOGICAL: case SHADER_OPCODE_URB_READ_SIMD8: |