diff options
| author | Rafael Antognolli <[email protected]> | 2019-11-05 11:11:53 -0800 |
|---|---|---|
| committer | Rafael Antognolli <[email protected]> | 2019-11-12 20:41:52 +0000 |
| commit | 2b01636ddb6d4f9bca7cb52ac599c3e143cdc39c (patch) | |
| tree | 57a628effbc678f3570088404234674667c2eedb /src/intel | |
| parent | d509a462254eb89002b729070f92d5708ac32afa (diff) | |
intel/isl: Add MOCS settings to isl_device.
Centralize mocs settings into isl.
Reviewed-by: Jordan Justen <[email protected]>
Acked-by: Lionel Landwerlin <[email protected]>
Diffstat (limited to 'src/intel')
| -rw-r--r-- | src/intel/isl/isl.c | 52 | ||||
| -rw-r--r-- | src/intel/isl/isl.h | 5 |
2 files changed, 57 insertions, 0 deletions
diff --git a/src/intel/isl/isl.c b/src/intel/isl/isl.c index 7c0d3c4dacd..54feaec6212 100644 --- a/src/intel/isl/isl.c +++ b/src/intel/isl/isl.c @@ -95,6 +95,56 @@ __isl_finishme(const char *file, int line, const char *fmt, ...) fprintf(stderr, "%s:%d: FINISHME: %s\n", file, line, buf); } +static void +isl_device_setup_mocs(struct isl_device *dev) +{ + if (dev->info->gen >= 12) { + /* TODO: Set PTE to MOCS 61 when the kernel is ready */ + /* TC=1/LLC Only, LeCC=1/Uncacheable, LRUM=0, L3CC=1/Uncacheable */ + dev->mocs.external = 3 << 1; + /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */ + dev->mocs.internal = 2 << 1; + } else if (dev->info->gen >= 9) { + /* TC=LLC/eLLC, LeCC=PTE, LRUM=3, L3CC=WB */ + dev->mocs.external = 1 << 1; + /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */ + dev->mocs.internal = 2 << 1; + } else if (dev->info->gen >= 8) { + /* MEMORY_OBJECT_CONTROL_STATE: + * .MemoryTypeLLCeLLCCacheabilityControl = UCwithFenceifcoherentcycle, + * .TargetCache = L3DefertoPATforLLCeLLCselection, + * .AgeforQUADLRU = 0 + */ + dev->mocs.external = 0x18; + /* MEMORY_OBJECT_CONTROL_STATE: + * .MemoryTypeLLCeLLCCacheabilityControl = WB, + * .TargetCache = L3DefertoPATforLLCeLLCselection, + * .AgeforQUADLRU = 0 + */ + dev->mocs.internal = 0x78; + } else if (dev->info->gen >= 7) { + if (dev->info->is_haswell) { + /* MEMORY_OBJECT_CONTROL_STATE: + * .LLCeLLCCacheabilityControlLLCCC = 0, + * .L3CacheabilityControlL3CC = 1, + */ + dev->mocs.internal = 1; + dev->mocs.external = 1; + } else { + /* MEMORY_OBJECT_CONTROL_STATE: + * .GraphicsDataTypeGFDT = 0, + * .LLCCacheabilityControlLLCCC = 0, + * .L3CacheabilityControlL3CC = 1, + */ + dev->mocs.internal = 1; + dev->mocs.external = 1; + } + } else { + dev->mocs.internal = 0; + dev->mocs.external = 0; + } +} + void isl_device_init(struct isl_device *dev, const struct gen_device_info *info, @@ -172,6 +222,8 @@ isl_device_init(struct isl_device *dev, dev->ds.stencil_offset = 0; dev->ds.hiz_offset = 0; } + + isl_device_setup_mocs(dev); } /** diff --git a/src/intel/isl/isl.h b/src/intel/isl/isl.h index 017052d79be..675ef1e33b1 100644 --- a/src/intel/isl/isl.h +++ b/src/intel/isl/isl.h @@ -1015,6 +1015,11 @@ struct isl_device { uint8_t stencil_offset; uint8_t hiz_offset; } ds; + + struct { + uint32_t internal; + uint32_t external; + } mocs; }; struct isl_extent2d { |