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authorAnuj Phogat <[email protected]>2017-05-19 12:13:40 -0700
committerAnuj Phogat <[email protected]>2018-02-15 16:14:55 -0800
commit0427bd4954acfd99c3b00b8a0993ca3c9e816d47 (patch)
tree5664eabede74c7a890ff5ac14cc06e06c42b3b84 /src/intel
parentc68ede0be765be882795ea23e4deac4539cf9b98 (diff)
intel/isl/icl: Add the maximum surface size limit
Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
Diffstat (limited to 'src/intel')
-rw-r--r--src/intel/isl/isl.c6
1 files changed, 5 insertions, 1 deletions
diff --git a/src/intel/isl/isl.c b/src/intel/isl/isl.c
index 59f512fc050..f70ac22aac5 100644
--- a/src/intel/isl/isl.c
+++ b/src/intel/isl/isl.c
@@ -1483,7 +1483,7 @@ isl_surf_init_s(const struct isl_device *dev,
*/
if (size > (uint64_t) 1 << 31)
return false;
- } else {
+ } else if (ISL_DEV_GEN(dev) < 11) {
/* From the Skylake PRM Vol 5, Maximum Surface Size in Bytes:
* "In addition to restrictions on maximum height, width, and depth,
* surfaces are also restricted to a maximum size of 2^38 bytes.
@@ -1492,6 +1492,10 @@ isl_surf_init_s(const struct isl_device *dev,
*/
if (size > (uint64_t) 1 << 38)
return false;
+ } else {
+ /* gen11+ platforms raised this limit to 2^44 bytes. */
+ if (size > (uint64_t) 1 << 44)
+ return false;
}
*surf = (struct isl_surf) {