nir: Get rid of nir_shader::stage

It's redundant with nir_shader::info::stage.

Acked-by: Timothy Arceri <[email protected]>
Reviewed-by: Kenneth Graunke <[email protected]>
Reviewed-by: Jordan Justen <[email protected]>

11 files changed, 38 insertions, 37 deletions

diff --git a/src/intel/blorp/blorp_priv.h b/src/intel/blorp/blorp_priv.h
index 7bbf0f04c20..c7d5d308da7 100644
--- a/src/intel/blorp/blorp_priv.h
+++ b/src/intel/blorp/blorp_priv.h
@@ -147,7 +147,7 @@ struct brw_blorp_wm_inputs
 #define BLORP_CREATE_NIR_INPUT(shader, name, type) ({ \
    nir_variable *input = nir_variable_create((shader), nir_var_shader_in, \
                                              type, #name); \
-   if ((shader)->stage == MESA_SHADER_FRAGMENT) \
+   if ((shader)->info.stage == MESA_SHADER_FRAGMENT) \
       input->data.interpolation = INTERP_MODE_FLAT; \
    input->data.location = VARYING_SLOT_VAR0 + \
       offsetof(struct brw_blorp_wm_inputs, name) / (4 * sizeof(float)); \
diff --git a/src/intel/compiler/brw_nir.c b/src/intel/compiler/brw_nir.c
index a04f4af7b08..327216eaaa7 100644
--- a/src/intel/compiler/brw_nir.c
+++ b/src/intel/compiler/brw_nir.c
@@ -165,7 +165,7 @@ remap_patch_urb_offsets(nir_block *block, nir_builder *b,
 
       nir_intrinsic_instr *intrin = nir_instr_as_intrinsic(instr);
 
-      gl_shader_stage stage = b->shader->stage;
+      gl_shader_stage stage = b->shader->info.stage;
 
       if ((stage == MESA_SHADER_TESS_CTRL && is_output(intrin)) ||
           (stage == MESA_SHADER_TESS_EVAL && is_input(intrin))) {
@@ -526,11 +526,11 @@ brw_nir_optimize(nir_shader *nir, const struct brw_compiler *compiler,
                  bool is_scalar)
 {
    nir_variable_mode indirect_mask = 0;
-   if (compiler->glsl_compiler_options[nir->stage].EmitNoIndirectInput)
+   if (compiler->glsl_compiler_options[nir->info.stage].EmitNoIndirectInput)
       indirect_mask |= nir_var_shader_in;
-   if (compiler->glsl_compiler_options[nir->stage].EmitNoIndirectOutput)
+   if (compiler->glsl_compiler_options[nir->info.stage].EmitNoIndirectOutput)
       indirect_mask |= nir_var_shader_out;
-   if (compiler->glsl_compiler_options[nir->stage].EmitNoIndirectTemp)
+   if (compiler->glsl_compiler_options[nir->info.stage].EmitNoIndirectTemp)
       indirect_mask |= nir_var_local;
 
    bool progress;
@@ -601,9 +601,9 @@ brw_preprocess_nir(const struct brw_compiler *compiler, nir_shader *nir)
    const struct gen_device_info *devinfo = compiler->devinfo;
    UNUSED bool progress; /* Written by OPT */
 
-   const bool is_scalar = compiler->scalar_stage[nir->stage];
+   const bool is_scalar = compiler->scalar_stage[nir->info.stage];
 
-   if (nir->stage == MESA_SHADER_GEOMETRY)
+   if (nir->info.stage == MESA_SHADER_GEOMETRY)
       OPT(nir_lower_gs_intrinsics);
 
    /* See also brw_nir_trig_workarounds.py */
@@ -638,11 +638,11 @@ brw_preprocess_nir(const struct brw_compiler *compiler, nir_shader *nir)
    OPT(nir_lower_clip_cull_distance_arrays);
 
    nir_variable_mode indirect_mask = 0;
-   if (compiler->glsl_compiler_options[nir->stage].EmitNoIndirectInput)
+   if (compiler->glsl_compiler_options[nir->info.stage].EmitNoIndirectInput)
       indirect_mask |= nir_var_shader_in;
-   if (compiler->glsl_compiler_options[nir->stage].EmitNoIndirectOutput)
+   if (compiler->glsl_compiler_options[nir->info.stage].EmitNoIndirectOutput)
       indirect_mask |= nir_var_shader_out;
-   if (compiler->glsl_compiler_options[nir->stage].EmitNoIndirectTemp)
+   if (compiler->glsl_compiler_options[nir->info.stage].EmitNoIndirectTemp)
       indirect_mask |= nir_var_local;
 
    nir_lower_indirect_derefs(nir, indirect_mask);
@@ -672,7 +672,7 @@ brw_postprocess_nir(nir_shader *nir, const struct brw_compiler *compiler,
 {
    const struct gen_device_info *devinfo = compiler->devinfo;
    bool debug_enabled =
-      (INTEL_DEBUG & intel_debug_flag_for_shader_stage(nir->stage));
+      (INTEL_DEBUG & intel_debug_flag_for_shader_stage(nir->info.stage));
 
    UNUSED bool progress; /* Written by OPT */
 
@@ -706,7 +706,7 @@ brw_postprocess_nir(nir_shader *nir, const struct brw_compiler *compiler,
       }
 
       fprintf(stderr, "NIR (SSA form) for %s shader:\n",
-              _mesa_shader_stage_to_string(nir->stage));
+              _mesa_shader_stage_to_string(nir->info.stage));
       nir_print_shader(nir, stderr);
    }
 
@@ -729,7 +729,7 @@ brw_postprocess_nir(nir_shader *nir, const struct brw_compiler *compiler,
 
    if (unlikely(debug_enabled)) {
       fprintf(stderr, "NIR (final form) for %s shader:\n",
-              _mesa_shader_stage_to_string(nir->stage));
+              _mesa_shader_stage_to_string(nir->info.stage));
       nir_print_shader(nir, stderr);
    }
 
diff --git a/src/intel/compiler/brw_nir_analyze_ubo_ranges.c b/src/intel/compiler/brw_nir_analyze_ubo_ranges.c
index 097aa8e62d6..32fbf8fccd9 100644
--- a/src/intel/compiler/brw_nir_analyze_ubo_ranges.c
+++ b/src/intel/compiler/brw_nir_analyze_ubo_ranges.c
@@ -172,7 +172,7 @@ brw_nir_analyze_ubo_ranges(const struct brw_compiler *compiler,
    const struct gen_device_info *devinfo = compiler->devinfo;
 
    if ((devinfo->gen <= 7 && !devinfo->is_haswell) ||
-       !compiler->scalar_stage[nir->stage]) {
+       !compiler->scalar_stage[nir->info.stage]) {
       memset(out_ranges, 0, 4 * sizeof(struct brw_ubo_range));
       return;
    }
diff --git a/src/intel/compiler/brw_nir_lower_cs_intrinsics.c b/src/intel/compiler/brw_nir_lower_cs_intrinsics.c
index 9b4a0fdf2eb..f9322654e7c 100644
--- a/src/intel/compiler/brw_nir_lower_cs_intrinsics.c
+++ b/src/intel/compiler/brw_nir_lower_cs_intrinsics.c
@@ -159,7 +159,7 @@ bool
 brw_nir_lower_cs_intrinsics(nir_shader *nir,
                             struct brw_cs_prog_data *prog_data)
 {
-   assert(nir->stage == MESA_SHADER_COMPUTE);
+   assert(nir->info.stage == MESA_SHADER_COMPUTE);
 
    bool progress = false;
    struct lower_intrinsics_state state;
diff --git a/src/intel/compiler/brw_nir_tcs_workarounds.c b/src/intel/compiler/brw_nir_tcs_workarounds.c
index a85f493c704..af7b7180431 100644
--- a/src/intel/compiler/brw_nir_tcs_workarounds.c
+++ b/src/intel/compiler/brw_nir_tcs_workarounds.c
@@ -123,7 +123,7 @@ emit_quads_workaround(nir_builder *b, nir_block *block)
 void
 brw_nir_apply_tcs_quads_workaround(nir_shader *nir)
 {
-   assert(nir->stage == MESA_SHADER_TESS_CTRL);
+   assert(nir->info.stage == MESA_SHADER_TESS_CTRL);
 
    nir_function_impl *impl = nir_shader_get_entrypoint(nir);
 
diff --git a/src/intel/compiler/brw_shader.cpp b/src/intel/compiler/brw_shader.cpp
index 4eb602b000a..7d62479fc63 100644
--- a/src/intel/compiler/brw_shader.cpp
+++ b/src/intel/compiler/brw_shader.cpp
@@ -670,7 +670,7 @@ backend_shader::backend_shader(const struct brw_compiler *compiler,
      stage_prog_data(stage_prog_data),
      mem_ctx(mem_ctx),
      cfg(NULL),
-     stage(shader->stage)
+     stage(shader->info.stage)
 {
    debug_enabled = INTEL_DEBUG & intel_debug_flag_for_shader_stage(stage);
    stage_name = _mesa_shader_stage_to_string(stage);
diff --git a/src/intel/compiler/brw_vec4_generator.cpp b/src/intel/compiler/brw_vec4_generator.cpp
index 6a3a0a080c3..bde4110e549 100644
--- a/src/intel/compiler/brw_vec4_generator.cpp
+++ b/src/intel/compiler/brw_vec4_generator.cpp
@@ -1497,9 +1497,9 @@ generate_code(struct brw_codegen *p,
               const struct cfg_t *cfg)
 {
    const struct gen_device_info *devinfo = p->devinfo;
-   const char *stage_abbrev = _mesa_shader_stage_to_abbrev(nir->stage);
+   const char *stage_abbrev = _mesa_shader_stage_to_abbrev(nir->info.stage);
    bool debug_flag = INTEL_DEBUG &
-      intel_debug_flag_for_shader_stage(nir->stage);
+      intel_debug_flag_for_shader_stage(nir->info.stage);
    struct annotation_info annotation;
    memset(&annotation, 0, sizeof(annotation));
    int spill_count = 0, fill_count = 0;
@@ -1770,7 +1770,7 @@ generate_code(struct brw_codegen *p,
       case SHADER_OPCODE_TG4:
       case SHADER_OPCODE_TG4_OFFSET:
       case SHADER_OPCODE_SAMPLEINFO:
-         generate_tex(p, prog_data, nir->stage,
+         generate_tex(p, prog_data, nir->info.stage,
                       inst, dst, src[0], src[1], src[2]);
          break;
 
@@ -1910,7 +1910,7 @@ generate_code(struct brw_codegen *p,
 
       case SHADER_OPCODE_FIND_LIVE_CHANNEL: {
          const struct brw_reg mask =
-            brw_stage_has_packed_dispatch(devinfo, nir->stage,
+            brw_stage_has_packed_dispatch(devinfo, nir->info.stage,
                                           &prog_data->base) ? brw_imm_ud(~0u) :
             brw_dmask_reg();
          brw_find_live_channel(p, dst, mask);
@@ -2195,7 +2195,7 @@ generate_code(struct brw_codegen *p,
    if (unlikely(debug_flag)) {
       fprintf(stderr, "Native code for %s %s shader %s:\n",
               nir->info.label ? nir->info.label : "unnamed",
-              _mesa_shader_stage_to_string(nir->stage), nir->info.name);
+              _mesa_shader_stage_to_string(nir->info.stage), nir->info.name);
 
       fprintf(stderr, "%s vec4 shader: %d instructions. %d loops. %u cycles. %d:%d "
                       "spills:fills. Compacted %d to %d bytes (%.0f%%)\n",
diff --git a/src/intel/vulkan/anv_nir_apply_pipeline_layout.c b/src/intel/vulkan/anv_nir_apply_pipeline_layout.c
index 3ca2b04049a..f8d81648a9a 100644
--- a/src/intel/vulkan/anv_nir_apply_pipeline_layout.c
+++ b/src/intel/vulkan/anv_nir_apply_pipeline_layout.c
@@ -296,6 +296,7 @@ anv_nir_apply_pipeline_layout(struct anv_pipeline *pipeline,
                               struct anv_pipeline_bind_map *map)
 {
    struct anv_pipeline_layout *layout = pipeline->layout;
+   gl_shader_stage stage = shader->info.stage;
 
    struct apply_pipeline_layout_state state = {
       .shader = shader,
@@ -328,15 +329,15 @@ anv_nir_apply_pipeline_layout(struct anv_pipeline *pipeline,
       BITSET_WORD b, _tmp;
       BITSET_FOREACH_SET(b, _tmp, state.set[set].used,
                          set_layout->binding_count) {
-         if (set_layout->binding[b].stage[shader->stage].surface_index >= 0) {
+         if (set_layout->binding[b].stage[stage].surface_index >= 0) {
             map->surface_count +=
                anv_descriptor_set_binding_layout_get_hw_size(&set_layout->binding[b]);
          }
-         if (set_layout->binding[b].stage[shader->stage].sampler_index >= 0) {
+         if (set_layout->binding[b].stage[stage].sampler_index >= 0) {
             map->sampler_count +=
                anv_descriptor_set_binding_layout_get_hw_size(&set_layout->binding[b]);
          }
-         if (set_layout->binding[b].stage[shader->stage].image_index >= 0)
+         if (set_layout->binding[b].stage[stage].image_index >= 0)
             map->image_count += set_layout->binding[b].array_size;
       }
    }
@@ -353,7 +354,7 @@ anv_nir_apply_pipeline_layout(struct anv_pipeline *pipeline,
          struct anv_descriptor_set_binding_layout *binding =
             &set_layout->binding[b];
 
-         if (binding->stage[shader->stage].surface_index >= 0) {
+         if (binding->stage[stage].surface_index >= 0) {
             state.set[set].surface_offsets[b] = surface;
             struct anv_sampler **samplers = binding->immutable_samplers;
             for (unsigned i = 0; i < binding->array_size; i++) {
@@ -368,7 +369,7 @@ anv_nir_apply_pipeline_layout(struct anv_pipeline *pipeline,
             }
          }
 
-         if (binding->stage[shader->stage].sampler_index >= 0) {
+         if (binding->stage[stage].sampler_index >= 0) {
             state.set[set].sampler_offsets[b] = sampler;
             struct anv_sampler **samplers = binding->immutable_samplers;
             for (unsigned i = 0; i < binding->array_size; i++) {
@@ -383,7 +384,7 @@ anv_nir_apply_pipeline_layout(struct anv_pipeline *pipeline,
             }
          }
 
-         if (binding->stage[shader->stage].image_index >= 0) {
+         if (binding->stage[stage].image_index >= 0) {
             state.set[set].image_offsets[b] = image;
             image += binding->array_size;
          }
diff --git a/src/intel/vulkan/anv_nir_lower_input_attachments.c b/src/intel/vulkan/anv_nir_lower_input_attachments.c
index 6ed7fafbf01..58b9b340a42 100644
--- a/src/intel/vulkan/anv_nir_lower_input_attachments.c
+++ b/src/intel/vulkan/anv_nir_lower_input_attachments.c
@@ -114,7 +114,7 @@ try_lower_input_load(nir_function_impl *impl, nir_intrinsic_instr *load)
 void
 anv_nir_lower_input_attachments(nir_shader *shader)
 {
-   assert(shader->stage == MESA_SHADER_FRAGMENT);
+   assert(shader->info.stage == MESA_SHADER_FRAGMENT);
 
    nir_foreach_function(function, shader) {
       if (!function->impl)
diff --git a/src/intel/vulkan/anv_nir_lower_multiview.c b/src/intel/vulkan/anv_nir_lower_multiview.c
index f40e1111492..88e6f9af877 100644
--- a/src/intel/vulkan/anv_nir_lower_multiview.c
+++ b/src/intel/vulkan/anv_nir_lower_multiview.c
@@ -44,7 +44,7 @@ struct lower_multiview_state {
 static nir_ssa_def *
 build_instance_id(struct lower_multiview_state *state)
 {
-   assert(state->builder.shader->stage == MESA_SHADER_VERTEX);
+   assert(state->builder.shader->info.stage == MESA_SHADER_VERTEX);
 
    if (state->instance_id == NULL) {
       nir_builder *b = &state->builder;
@@ -74,7 +74,7 @@ build_view_index(struct lower_multiview_state *state)
       assert(state->view_mask != 0);
       if (0 && _mesa_bitcount(state->view_mask) == 1) {
          state->view_index = nir_imm_int(b, ffs(state->view_mask) - 1);
-      } else if (state->builder.shader->stage == MESA_SHADER_VERTEX) {
+      } else if (state->builder.shader->info.stage == MESA_SHADER_VERTEX) {
          /* We only support 16 viewports */
          assert((state->view_mask & 0xffff0000) == 0);
 
@@ -122,15 +122,15 @@ build_view_index(struct lower_multiview_state *state)
          }
       } else {
          const struct glsl_type *type = glsl_int_type();
-         if (b->shader->stage == MESA_SHADER_TESS_CTRL ||
-             b->shader->stage == MESA_SHADER_GEOMETRY)
+         if (b->shader->info.stage == MESA_SHADER_TESS_CTRL ||
+             b->shader->info.stage == MESA_SHADER_GEOMETRY)
             type = glsl_array_type(type, 1);
 
          nir_variable *idx_var =
             nir_variable_create(b->shader, nir_var_shader_in,
                                 type, "view index");
          idx_var->data.location = VARYING_SLOT_VIEW_INDEX;
-         if (b->shader->stage == MESA_SHADER_FRAGMENT)
+         if (b->shader->info.stage == MESA_SHADER_FRAGMENT)
             idx_var->data.interpolation = INTERP_MODE_FLAT;
 
          if (glsl_type_is_array(type)) {
@@ -154,7 +154,7 @@ build_view_index(struct lower_multiview_state *state)
 bool
 anv_nir_lower_multiview(nir_shader *shader, uint32_t view_mask)
 {
-   assert(shader->stage != MESA_SHADER_COMPUTE);
+   assert(shader->info.stage != MESA_SHADER_COMPUTE);
 
    /* If multiview isn't enabled, we have nothing to do. */
    if (view_mask == 0)
@@ -202,7 +202,7 @@ anv_nir_lower_multiview(nir_shader *shader, uint32_t view_mask)
     * available in the VS.  If it's not a fragment shader, we need to pass
     * the view index on to the next stage.
     */
-   if (shader->stage != MESA_SHADER_FRAGMENT) {
+   if (shader->info.stage != MESA_SHADER_FRAGMENT) {
       nir_ssa_def *view_index = build_view_index(&state);
 
       nir_builder *b = &state.builder;
diff --git a/src/intel/vulkan/anv_pipeline.c b/src/intel/vulkan/anv_pipeline.c
index 7bfdb5c5509..51788928af8 100644
--- a/src/intel/vulkan/anv_pipeline.c
+++ b/src/intel/vulkan/anv_pipeline.c
@@ -138,7 +138,7 @@ anv_shader_compile_to_nir(struct anv_pipeline *pipeline,
                    spec_entries, num_spec_entries,
                    stage, entrypoint_name, &supported_ext, nir_options);
    nir_shader *nir = entry_point->shader;
-   assert(nir->stage == stage);
+   assert(nir->info.stage == stage);
    nir_validate_shader(nir);
    ralloc_steal(mem_ctx, nir);