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authorJason Ekstrand <[email protected]>2017-12-15 11:27:39 -0800
committerJason Ekstrand <[email protected]>2018-01-23 21:10:08 -0800
commit4b69ba381766cd911eb1284f1b0332a139ec8a75 (patch)
tree9df51d696900260c44ff6e8b8191b4dc5e468bfb /src/intel
parent766589d89a211e67f313e8cb38f2d05b09975f96 (diff)
anv/pipeline: Don't assert on more than 32 samplers
This prevents an assert when running one unreleased Vulkan game. Tested-by: Józef Kucia <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]> Cc: "18.0" <[email protected]>
Diffstat (limited to 'src/intel')
-rw-r--r--src/intel/vulkan/genX_pipeline.c8
1 files changed, 7 insertions, 1 deletions
diff --git a/src/intel/vulkan/genX_pipeline.c b/src/intel/vulkan/genX_pipeline.c
index cfc3bea4265..82fdf206a95 100644
--- a/src/intel/vulkan/genX_pipeline.c
+++ b/src/intel/vulkan/genX_pipeline.c
@@ -1081,7 +1081,13 @@ emit_3dstate_streamout(struct anv_pipeline *pipeline,
static uint32_t
get_sampler_count(const struct anv_shader_bin *bin)
{
- return DIV_ROUND_UP(bin->bind_map.sampler_count, 4);
+ uint32_t count_by_4 = DIV_ROUND_UP(bin->bind_map.sampler_count, 4);
+
+ /* We can potentially have way more than 32 samplers and that's ok.
+ * However, the 3DSTATE_XS packets only have 3 bits to specify how
+ * many to pre-fetch and all values above 4 are marked reserved.
+ */
+ return MIN2(count_by_4, 4);
}
static uint32_t