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authorIván Briano <[email protected]>2019-10-23 09:18:03 -0700
committerIván Briano <[email protected]>2019-11-18 14:19:41 -0800
commitca94717035f695fd25dd07bb16167c12520d86c3 (patch)
tree24b8956eaf7492455fb66b2ca6b240c76b03efd9 /src/intel
parent3cd44839faa605590790a22d07123ec6d797c4ca (diff)
intel/compiler: Don't change hstride if not needed
Alignment requirements may have changed the horizontal stride already, so don't set it if not required to avoid breaking said requirements. Fixes several tests such as dEQP-VK.subgroups.vote.graphics.subgroupallequal_int8_t Signed-off-by: Iván Briano <[email protected]> Reviewed-by: Paulo Zanoni <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
Diffstat (limited to 'src/intel')
-rw-r--r--src/intel/compiler/brw_eu_emit.c11
1 files changed, 6 insertions, 5 deletions
diff --git a/src/intel/compiler/brw_eu_emit.c b/src/intel/compiler/brw_eu_emit.c
index ecd3c34470c..44577de62e8 100644
--- a/src/intel/compiler/brw_eu_emit.c
+++ b/src/intel/compiler/brw_eu_emit.c
@@ -95,14 +95,15 @@ brw_set_dest(struct brw_codegen *p, brw_inst *inst, struct brw_reg dest)
else if (dest.file == BRW_GENERAL_REGISTER_FILE)
assert(dest.nr < 128);
- /* The hardware has a restriction where if the destination is Byte,
- * the instruction needs to have a stride of 2 (except for packed byte
- * MOV). This seems to be required even if the destination is the NULL
- * register.
+ /* The hardware has a restriction where a destination of size Byte with
+ * a stride of 1 is only allowed for a packed byte MOV. For any other
+ * instruction, the stride must be at least 2, even when the destination
+ * is the NULL register.
*/
if (dest.file == BRW_ARCHITECTURE_REGISTER_FILE &&
dest.nr == BRW_ARF_NULL &&
- type_sz(dest.type) == 1) {
+ type_sz(dest.type) == 1 &&
+ dest.hstride == BRW_HORIZONTAL_STRIDE_1) {
dest.hstride = BRW_HORIZONTAL_STRIDE_2;
}