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authorLionel Landwerlin <[email protected]>2018-03-27 17:56:44 +0100
committerLionel Landwerlin <[email protected]>2018-04-03 16:55:53 +0100
commitb3aa18dfd6fd343b45c1138e545d1130046bcb91 (patch)
treeab4f0ebad515b4be3113ea32d29a3b6bacae91ec /src/intel
parent6f6e711c721eba8dad1541479e31d5db5108b41d (diff)
intel: genxml: add preemption control instructions
Helpful to debug kernel workaround batchbuffers. Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Scott D Phillips <[email protected]>
Diffstat (limited to 'src/intel')
-rw-r--r--src/intel/genxml/gen10.xml7
-rw-r--r--src/intel/genxml/gen11.xml7
-rw-r--r--src/intel/genxml/gen8.xml6
-rw-r--r--src/intel/genxml/gen9.xml6
4 files changed, 26 insertions, 0 deletions
diff --git a/src/intel/genxml/gen10.xml b/src/intel/genxml/gen10.xml
index aeb99667592..bd914ad10ee 100644
--- a/src/intel/genxml/gen10.xml
+++ b/src/intel/genxml/gen10.xml
@@ -2824,6 +2824,13 @@
<field name="MI Command Opcode" start="23" end="28" type="uint" default="5"/>
</instruction>
+ <instruction name="MI_ARB_ON_OFF" bias="1" length="1">
+ <field name="Command Type" start="29" end="31" type="uint" default="0"/>
+ <field name="MI Command Opcode" start="23" end="28" type="uint" default="8"/>
+ <field name="Allow Lite Restore" start="1" end="1" type="bool"/>
+ <field name="Arbitration Enable" start="0" end="0" type="bool" default="1"/>
+ </instruction>
+
<instruction name="MI_ATOMIC" bias="2" length="3">
<field name="Command Type" start="29" end="31" type="uint" default="0"/>
<field name="MI Command Opcode" start="23" end="28" type="uint" default="47"/>
diff --git a/src/intel/genxml/gen11.xml b/src/intel/genxml/gen11.xml
index 6ca0e785ba0..cb3212620f5 100644
--- a/src/intel/genxml/gen11.xml
+++ b/src/intel/genxml/gen11.xml
@@ -2788,6 +2788,13 @@
<field name="MI Command Opcode" start="23" end="28" type="uint" default="5"/>
</instruction>
+ <instruction name="MI_ARB_ON_OFF" bias="1" length="1">
+ <field name="Command Type" start="29" end="31" type="uint" default="0"/>
+ <field name="MI Command Opcode" start="23" end="28" type="uint" default="8"/>
+ <field name="Allow Lite Restore" start="1" end="1" type="bool"/>
+ <field name="Arbitration Enable" start="0" end="0" type="bool" default="1"/>
+ </instruction>
+
<instruction name="MI_ATOMIC" bias="2" length="3">
<field name="Command Type" start="29" end="31" type="uint" default="0"/>
<field name="MI Command Opcode" start="23" end="28" type="uint" default="47"/>
diff --git a/src/intel/genxml/gen8.xml b/src/intel/genxml/gen8.xml
index 71626c15cd2..28fbdfdf09a 100644
--- a/src/intel/genxml/gen8.xml
+++ b/src/intel/genxml/gen8.xml
@@ -2509,6 +2509,12 @@
<field name="MI Command Opcode" start="23" end="28" type="uint" default="5"/>
</instruction>
+ <instruction name="MI_ARB_ON_OFF" bias="1" length="1">
+ <field name="Command Type" start="29" end="31" type="uint" default="0"/>
+ <field name="MI Command Opcode" start="23" end="28" type="uint" default="8"/>
+ <field name="Arbitration Enable" start="0" end="0" type="bool" default="1"/>
+ </instruction>
+
<instruction name="MI_ATOMIC" bias="2" length="3">
<field name="Command Type" start="29" end="31" type="uint" default="0"/>
<field name="MI Command Opcode" start="23" end="28" type="uint" default="47"/>
diff --git a/src/intel/genxml/gen9.xml b/src/intel/genxml/gen9.xml
index c32f2c3162c..0912b6f7fe4 100644
--- a/src/intel/genxml/gen9.xml
+++ b/src/intel/genxml/gen9.xml
@@ -2752,6 +2752,12 @@
<field name="MI Command Opcode" start="23" end="28" type="uint" default="5"/>
</instruction>
+ <instruction name="MI_ARB_ON_OFF" bias="1" length="1">
+ <field name="Command Type" start="29" end="31" type="uint" default="0"/>
+ <field name="MI Command Opcode" start="23" end="28" type="uint" default="8"/>
+ <field name="Arbitration Enable" start="0" end="0" type="bool" default="1"/>
+ </instruction>
+
<instruction name="MI_ATOMIC" bias="2" length="3">
<field name="Command Type" start="29" end="31" type="uint" default="0"/>
<field name="MI Command Opcode" start="23" end="28" type="uint" default="47"/>