diff options
author | Jason Ekstrand <[email protected]> | 2017-08-22 18:57:56 -0700 |
---|---|---|
committer | Jason Ekstrand <[email protected]> | 2017-11-07 10:37:52 -0800 |
commit | ab9220edd69fcb7016e15d4d96186eac524b45a4 (patch) | |
tree | 9814f05cb0ebd2154752d48ea72b48c6ad1a21c0 /src/intel | |
parent | a026458020e947cc5d864cfb5b19660836b2d613 (diff) |
nir,intel/compiler: Use a fixed subgroup size
The GL_ARB_shader_ballot spec says that gl_SubGroupSizeARB is declared
as a uniform. This means that it cannot change across an invocation
such as a draw call or a compute dispatch. For compute shaders, we're
ok because we only ever use one dispatch size. For fragment, however,
the hardware dynamically chooses between SIMD8 and SIMD16 which violates
the spec. Instead, let's just pick a subgroup size based on the shader
stage. The fixed size we choose for compute shaders is a bit higher
than strictly needed but there's no real harm in that. The advantage is
that, if they do anything interesting with the value, NIR will see it as
an immediate and can optimize better.
Acked-by: Lionel Landwerlin <[email protected]>
Reviewed-by: Iago Toral Quiroga <[email protected]>
Diffstat (limited to 'src/intel')
-rw-r--r-- | src/intel/compiler/brw_fs_nir.cpp | 4 | ||||
-rw-r--r-- | src/intel/compiler/brw_nir.c | 2 |
2 files changed, 2 insertions, 4 deletions
diff --git a/src/intel/compiler/brw_fs_nir.cpp b/src/intel/compiler/brw_fs_nir.cpp index f8970997371..2f47b0253b2 100644 --- a/src/intel/compiler/brw_fs_nir.cpp +++ b/src/intel/compiler/brw_fs_nir.cpp @@ -4184,10 +4184,6 @@ fs_visitor::nir_emit_intrinsic(const fs_builder &bld, nir_intrinsic_instr *instr break; } - case nir_intrinsic_load_subgroup_size: - bld.MOV(retype(dest, BRW_REGISTER_TYPE_D), brw_imm_d(dispatch_width)); - break; - case nir_intrinsic_load_subgroup_invocation: bld.MOV(retype(dest, BRW_REGISTER_TYPE_D), nir_system_values[SYSTEM_VALUE_SUBGROUP_INVOCATION]); diff --git a/src/intel/compiler/brw_nir.c b/src/intel/compiler/brw_nir.c index 0d59d36ca63..5ed36fe1bf7 100644 --- a/src/intel/compiler/brw_nir.c +++ b/src/intel/compiler/brw_nir.c @@ -637,6 +637,8 @@ brw_preprocess_nir(const struct brw_compiler *compiler, nir_shader *nir) OPT(nir_lower_system_values); const nir_lower_subgroups_options subgroups_options = { + .subgroup_size = nir->info.stage == MESA_SHADER_COMPUTE ? 32 : + nir->info.stage == MESA_SHADER_FRAGMENT ? 16 : 8, .ballot_bit_size = 32, .lower_to_scalar = true, .lower_subgroup_masks = true, |