diff options
| author | Jason Ekstrand <[email protected]> | 2020-03-18 13:29:06 -0500 |
|---|---|---|
| committer | Marge Bot <[email protected]> | 2020-03-19 21:58:49 +0000 |
| commit | 3252041a7872c49e53bb02ffe8b079b5fc43f15e (patch) | |
| tree | a1ee50846170a114bcc1eb8b89f508b9ead04067 /src/intel | |
| parent | 5b57aa79e2bd244079639bcc696251ce0f7af7c7 (diff) | |
anv: Only add END_OF_PIPE_SYNC if we actually have AUX_INVAL
Fixes: 43dc842cb91c "anv: Wait for the GPU to be idle before..."
Reviewed-by: Rafael Antognolli <[email protected]>
Reviewed-by: D Scott Phillips <[email protected]>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4234>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4234>
Diffstat (limited to 'src/intel')
| -rw-r--r-- | src/intel/vulkan/genX_cmd_buffer.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/intel/vulkan/genX_cmd_buffer.c b/src/intel/vulkan/genX_cmd_buffer.c index c60d156d522..2c5a448aff3 100644 --- a/src/intel/vulkan/genX_cmd_buffer.c +++ b/src/intel/vulkan/genX_cmd_buffer.c @@ -2042,7 +2042,7 @@ genX(cmd_buffer_apply_pipe_flushes)(struct anv_cmd_buffer *cmd_buffer) * add extra flushes in the case it knows that the engine is already * IDLE." */ - if (GEN_GEN == 12 && ANV_PIPE_AUX_TABLE_INVALIDATE_BIT) + if (GEN_GEN == 12 && (bits & ANV_PIPE_AUX_TABLE_INVALIDATE_BIT)) bits |= ANV_PIPE_NEEDS_END_OF_PIPE_SYNC_BIT; /* If we're going to do an invalidate and we have a pending end-of-pipe |