summaryrefslogtreecommitdiffstats
path: root/src/intel
diff options
context:
space:
mode:
authorConnor Abbott <[email protected]>2019-05-13 15:39:54 +0200
committerConnor Abbott <[email protected]>2019-07-08 14:14:53 +0200
commit27f0c3c15ef753bf5eb089c725341790e9693c53 (patch)
tree7832183b3cf5d2f7e9fb482a67ce8df1d128dafe /src/intel
parent64f3fc5ea6a0487e553fe1bfedacff3c3697ab54 (diff)
radv: Make FragCoord a sysval
load_fragcoord is already handled in common code for radeonsi, so we don't need to do anything to handle it. However, there were some passes creating NIR with the varying, so we switch them over to the sysval. In the case of nir_lower_input_attachments which is used by both radv and anv, we add handling for both until intel switches to using a sysval. Reviewed-by: Bas Nieuwenhuizen <[email protected]>
Diffstat (limited to 'src/intel')
-rw-r--r--src/intel/vulkan/anv_pipeline.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/intel/vulkan/anv_pipeline.c b/src/intel/vulkan/anv_pipeline.c
index 8fa02aedfa1..051c3334aa8 100644
--- a/src/intel/vulkan/anv_pipeline.c
+++ b/src/intel/vulkan/anv_pipeline.c
@@ -607,7 +607,7 @@ anv_pipeline_lower_nir(struct anv_pipeline *pipeline,
if (nir->info.stage == MESA_SHADER_FRAGMENT) {
NIR_PASS_V(nir, nir_lower_wpos_center, pipeline->sample_shading_enable);
- NIR_PASS_V(nir, nir_lower_input_attachments);
+ NIR_PASS_V(nir, nir_lower_input_attachments, false);
}
NIR_PASS_V(nir, anv_nir_lower_ycbcr_textures, layout);