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| author | Eric Anholt <[email protected]> | 2018-03-30 16:31:07 -0700 |
|---|---|---|
| committer | Eric Anholt <[email protected]> | 2018-04-12 11:20:50 -0700 |
| commit | 8f2999120de83845b1c0098170356819c5a6e439 (patch) | |
| tree | 76d728159e26cb104615fb8a8695dae1d3b831dd /src/intel | |
| parent | 7553cbfc9d78f0a4f8816122ce6327bc3899c2b5 (diff) | |
broadcom/vc5: Add checks that we don't try to do raw Z+S load/stores.
This was dying in the simulator on
GTF-GLES3.gtf.GL3Tests.packed_depth_stencil.packed_depth_stencil_blit.
We'll need to do basically the same thing as Z32F/S8 does in the MSAA
Z24S8 case.
Diffstat (limited to 'src/intel')
0 files changed, 0 insertions, 0 deletions