diff options
| author | Rafael Antognolli <[email protected]> | 2017-10-06 11:41:54 -0700 |
|---|---|---|
| committer | Rafael Antognolli <[email protected]> | 2017-12-01 11:27:27 -0800 |
| commit | 2919adffe9f8ac4ea9e152db45c410cdc4514b7d (patch) | |
| tree | b6b45627bc23b9b6cf5045208297b0d4c7a81aed /src/intel | |
| parent | 979fc1bc9bcc64027ff2cfafd285676f31b930a6 (diff) | |
intel/compiler: Implement WaClearTDRRegBeforeEOTForNonPS.
The bspec describes:
"WA: Clear tdr register before send EOT in all non-PS shader kernels
mov(8) tdr0:ud 0x0:ud {NoMask}"
Signed-off-by: Rafael Antognolli <[email protected]>
Reviewed-by: Kenneth Graunke <[email protected]>
Diffstat (limited to 'src/intel')
| -rw-r--r-- | src/intel/compiler/brw_fs_generator.cpp | 13 | ||||
| -rw-r--r-- | src/intel/compiler/brw_reg.h | 6 |
2 files changed, 19 insertions, 0 deletions
diff --git a/src/intel/compiler/brw_fs_generator.cpp b/src/intel/compiler/brw_fs_generator.cpp index 28790c86a64..4f90ec9dfff 100644 --- a/src/intel/compiler/brw_fs_generator.cpp +++ b/src/intel/compiler/brw_fs_generator.cpp @@ -573,6 +573,19 @@ fs_generator::generate_urb_write(fs_inst *inst, struct brw_reg payload) { brw_inst *insn; + /* WaClearTDRRegBeforeEOTForNonPS. + * + * WA: Clear tdr register before send EOT in all non-PS shader kernels + * + * mov(8) tdr0:ud 0x0:ud {NoMask}" + */ + if (inst->eot && p->devinfo->gen == 10) { + brw_push_insn_state(p); + brw_set_default_mask_control(p, BRW_MASK_DISABLE); + brw_MOV(p, brw_tdr_reg(), brw_imm_uw(0)); + brw_pop_insn_state(p); + } + insn = brw_next_insn(p, BRW_OPCODE_SEND); brw_set_dest(p, insn, brw_null_reg()); diff --git a/src/intel/compiler/brw_reg.h b/src/intel/compiler/brw_reg.h index ec1045b612a..a039c6f676c 100644 --- a/src/intel/compiler/brw_reg.h +++ b/src/intel/compiler/brw_reg.h @@ -774,6 +774,12 @@ brw_address_reg(unsigned subnr) return brw_uw1_reg(BRW_ARCHITECTURE_REGISTER_FILE, BRW_ARF_ADDRESS, subnr); } +static inline struct brw_reg +brw_tdr_reg(void) +{ + return brw_uw1_reg(BRW_ARCHITECTURE_REGISTER_FILE, BRW_ARF_TDR, 0); +} + /* If/else instructions break in align16 mode if writemask & swizzle * aren't xyzw. This goes against the convention for other scalar * regs: |