diff options
| author | Nanley Chery <[email protected]> | 2016-09-22 14:51:37 -0700 |
|---|---|---|
| committer | Nanley Chery <[email protected]> | 2016-11-03 11:22:58 -0700 |
| commit | faab6a0f18825bd1bd3a6f0cfc4e4e68e041b6e2 (patch) | |
| tree | 79439ae0aa49f7759bd552fc8ee6a0a8287de169 /src/intel | |
| parent | 1625d911d7368a9a96411012c69512074a3ff506 (diff) | |
isl: Only allow Y-tiling for ASTC textures
Signed-off-by: Nanley Chery <[email protected]>
Reviewed-by: Jason Ekstrand <[email protected]>
Diffstat (limited to 'src/intel')
| -rw-r--r-- | src/intel/isl/isl_gen7.c | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/src/intel/isl/isl_gen7.c b/src/intel/isl/isl_gen7.c index b6a86d23f37..18687b535de 100644 --- a/src/intel/isl/isl_gen7.c +++ b/src/intel/isl/isl_gen7.c @@ -215,6 +215,12 @@ isl_gen6_filter_tiling(const struct isl_device *dev, *flags &= ~ISL_TILING_W_BIT; } + /* From the SKL+ PRMs, RENDER_SURFACE_STATE:TileMode, + * If Surface Format is ASTC*, this field must be TILEMODE_YMAJOR. + */ + if (isl_format_get_layout(info->format)->txc == ISL_TXC_ASTC) + *flags &= ISL_TILING_Y0_BIT; + /* MCS buffers are always Y-tiled */ if (isl_format_get_layout(info->format)->txc == ISL_TXC_MCS) *flags &= ISL_TILING_Y0_BIT; |