summaryrefslogtreecommitdiffstats
path: root/src/intel
diff options
context:
space:
mode:
authorJason Ekstrand <[email protected]>2017-02-01 12:27:59 -0800
committerJason Ekstrand <[email protected]>2017-02-01 14:41:06 -0800
commitccdd5b3738ef23dc69f322b9deab290cfaa1d0c5 (patch)
tree403fa1fb0948bf3734e9056389f63c9681436db4 /src/intel
parent752ae38a0981f5799f2445fced4f19cbcab8baad (diff)
anv: Don't use bogus alpha swizzles
For RGB formats in Vulkan, we use the corresponding RGBA format with a swizzle of RGB1. While this swizzle is exactly what we want for texturing, it's not allowed for rendering according to the docs. While we haven't been getting hangs or anything, we should probably obey the docs. This commit just sanitizes all render swizzles so that the alpha channel maps to ALPHA. Reviewed-by: Anuj Phogat <[email protected]>
Diffstat (limited to 'src/intel')
-rw-r--r--src/intel/vulkan/anv_blorp.c9
-rw-r--r--src/intel/vulkan/anv_private.h15
-rw-r--r--src/intel/vulkan/genX_cmd_buffer.c1
3 files changed, 22 insertions, 3 deletions
diff --git a/src/intel/vulkan/anv_blorp.c b/src/intel/vulkan/anv_blorp.c
index 2edd0712c95..2cf972bb613 100644
--- a/src/intel/vulkan/anv_blorp.c
+++ b/src/intel/vulkan/anv_blorp.c
@@ -503,7 +503,8 @@ void anv_CmdBlitImage(
blorp_blit(&batch, &src, src_res->mipLevel, src_z,
src_format.isl_format, src_format.swizzle,
&dst, dst_res->mipLevel, dst_z,
- dst_format.isl_format, dst_format.swizzle,
+ dst_format.isl_format,
+ anv_swizzle_for_render(dst_format.swizzle),
src_x0, src_y0, src_x1, src_y1,
dst_x0, dst_y0, dst_x1, dst_y1,
gl_filter, flip_x, flip_y);
@@ -831,7 +832,8 @@ void anv_CmdClearColorImage(
}
blorp_clear(&batch, &surf,
- src_format.isl_format, src_format.swizzle,
+ src_format.isl_format,
+ anv_swizzle_for_render(src_format.swizzle),
level, base_layer, layer_count,
0, 0, level_width, level_height,
vk_to_isl_color(*pColor), color_write_disable);
@@ -1216,7 +1218,8 @@ anv_cmd_buffer_clear_subpass(struct anv_cmd_buffer *cmd_buffer)
cmd_buffer->state.pending_pipe_bits |=
ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT | ANV_PIPE_CS_STALL_BIT;
} else {
- blorp_clear(&batch, &surf, iview->isl.format, iview->isl.swizzle,
+ blorp_clear(&batch, &surf, iview->isl.format,
+ anv_swizzle_for_render(iview->isl.swizzle),
iview->isl.base_level,
iview->isl.base_array_layer, fb->layers,
render_area.offset.x, render_area.offset.y,
diff --git a/src/intel/vulkan/anv_private.h b/src/intel/vulkan/anv_private.h
index 0cc6550a402..a0cb35ccccb 100644
--- a/src/intel/vulkan/anv_private.h
+++ b/src/intel/vulkan/anv_private.h
@@ -1552,6 +1552,21 @@ anv_get_isl_format(const struct gen_device_info *devinfo, VkFormat vk_format,
return anv_get_format(devinfo, vk_format, aspect, tiling).isl_format;
}
+static inline struct isl_swizzle
+anv_swizzle_for_render(struct isl_swizzle swizzle)
+{
+ /* Sometimes the swizzle will have alpha map to one. We do this to fake
+ * RGB as RGBA for texturing
+ */
+ assert(swizzle.a == ISL_CHANNEL_SELECT_ONE ||
+ swizzle.a == ISL_CHANNEL_SELECT_ALPHA);
+
+ /* But it doesn't matter what we render to that channel */
+ swizzle.a = ISL_CHANNEL_SELECT_ALPHA;
+
+ return swizzle;
+}
+
void
anv_pipeline_setup_l3_config(struct anv_pipeline *pipeline, bool needs_slm);
diff --git a/src/intel/vulkan/genX_cmd_buffer.c b/src/intel/vulkan/genX_cmd_buffer.c
index 0ad7cd5538a..b6b7f7475ce 100644
--- a/src/intel/vulkan/genX_cmd_buffer.c
+++ b/src/intel/vulkan/genX_cmd_buffer.c
@@ -528,6 +528,7 @@ genX(cmd_buffer_setup_attachments)(struct anv_cmd_buffer *cmd_buffer,
struct isl_view view = iview->isl;
view.usage |= ISL_SURF_USAGE_RENDER_TARGET_BIT;
+ view.swizzle = anv_swizzle_for_render(view.swizzle);
isl_surf_fill_state(isl_dev,
state->attachments[i].color_rt_state.map,
.surf = &iview->image->color_surface.isl,