diff options
| author | Antia Puentes <[email protected]> | 2018-01-25 19:15:40 +0100 |
|---|---|---|
| committer | Ian Romanick <[email protected]> | 2018-04-19 15:57:45 -0700 |
| commit | c32e1035cb4f1e0c2c1bd45611e3a35e7caf57b6 (patch) | |
| tree | a595d9f358826f587350ffd8366b76de4c7d47c8 /src/intel | |
| parent | 0c8395e15d295d328f68574e71afaf04596e2a82 (diff) | |
intel: Handle firstvertex in an identical way to BaseVertex
Until we set gl_BaseVertex to zero for non-indexed draw calls
both have an identical value.
The Vertex Elements are kept like that:
* VE 1: <BaseVertex/firstvertex, BaseInstance, VertexID, InstanceID>
* VE 2: <Draw ID, 0, 0, 0>
v2 (idr): Mark nir_intrinsic_load_first_vertex as "unreachable" in
emit_system_values_block and fs_visitor::nir_emit_vs_intrinsic.
Diffstat (limited to 'src/intel')
| -rw-r--r-- | src/intel/compiler/brw_fs_nir.cpp | 4 | ||||
| -rw-r--r-- | src/intel/compiler/brw_nir.c | 3 | ||||
| -rw-r--r-- | src/intel/compiler/brw_vec4.cpp | 1 |
3 files changed, 8 insertions, 0 deletions
diff --git a/src/intel/compiler/brw_fs_nir.cpp b/src/intel/compiler/brw_fs_nir.cpp index 6c4bcd1c113..a830bb9fcd6 100644 --- a/src/intel/compiler/brw_fs_nir.cpp +++ b/src/intel/compiler/brw_fs_nir.cpp @@ -116,6 +116,7 @@ emit_system_values_block(nir_block *block, fs_visitor *v) case nir_intrinsic_load_vertex_id_zero_base: case nir_intrinsic_load_base_vertex: + case nir_intrinsic_load_first_vertex: case nir_intrinsic_load_instance_id: case nir_intrinsic_load_base_instance: case nir_intrinsic_load_draw_id: @@ -2458,6 +2459,9 @@ fs_visitor::nir_emit_vs_intrinsic(const fs_builder &bld, break; } + case nir_intrinsic_load_first_vertex: + unreachable("lowered by brw_nir_lower_vs_inputs"); + default: nir_emit_intrinsic(bld, instr); break; diff --git a/src/intel/compiler/brw_nir.c b/src/intel/compiler/brw_nir.c index 69ab162f888..16b0d86814f 100644 --- a/src/intel/compiler/brw_nir.c +++ b/src/intel/compiler/brw_nir.c @@ -239,6 +239,7 @@ brw_nir_lower_vs_inputs(nir_shader *nir, const bool has_sgvs = nir->info.system_values_read & (BITFIELD64_BIT(SYSTEM_VALUE_BASE_VERTEX) | + BITFIELD64_BIT(SYSTEM_VALUE_FIRST_VERTEX) | BITFIELD64_BIT(SYSTEM_VALUE_BASE_INSTANCE) | BITFIELD64_BIT(SYSTEM_VALUE_VERTEX_ID_ZERO_BASE) | BITFIELD64_BIT(SYSTEM_VALUE_INSTANCE_ID)); @@ -261,6 +262,7 @@ brw_nir_lower_vs_inputs(nir_shader *nir, switch (intrin->intrinsic) { case nir_intrinsic_load_base_vertex: + case nir_intrinsic_load_first_vertex: case nir_intrinsic_load_base_instance: case nir_intrinsic_load_vertex_id_zero_base: case nir_intrinsic_load_instance_id: @@ -278,6 +280,7 @@ brw_nir_lower_vs_inputs(nir_shader *nir, nir_intrinsic_set_base(load, num_inputs); switch (intrin->intrinsic) { case nir_intrinsic_load_base_vertex: + case nir_intrinsic_load_first_vertex: nir_intrinsic_set_component(load, 0); break; case nir_intrinsic_load_base_instance: diff --git a/src/intel/compiler/brw_vec4.cpp b/src/intel/compiler/brw_vec4.cpp index 9459d61af6c..1e384f5bf4d 100644 --- a/src/intel/compiler/brw_vec4.cpp +++ b/src/intel/compiler/brw_vec4.cpp @@ -2826,6 +2826,7 @@ brw_compile_vs(const struct brw_compiler *compiler, void *log_data, */ if (shader->info.system_values_read & (BITFIELD64_BIT(SYSTEM_VALUE_BASE_VERTEX) | + BITFIELD64_BIT(SYSTEM_VALUE_FIRST_VERTEX) | BITFIELD64_BIT(SYSTEM_VALUE_BASE_INSTANCE) | BITFIELD64_BIT(SYSTEM_VALUE_VERTEX_ID_ZERO_BASE) | BITFIELD64_BIT(SYSTEM_VALUE_INSTANCE_ID))) { |